Hi Joerg,
Do you have any further comment on this patch?
Thanks
Yian
On 10/17/2019 4:39 AM, Yian Chen wrote:
VT-d RMRR (Reserved Memory Region Reporting) regions are reserved
for device use only and should not be part of allocable memory pool of OS.
BIOS e820_table reports complete memory
On 12/16/2019 11:35 AM, Barret Rhoden wrote:
On 12/16/19 2:07 PM, Chen, Yian wrote:
On 12/11/2019 11:46 AM, Barret Rhoden wrote:
RMRR entries describe memory regions that are DMA targets for devices
outside the kernel's control.
RMRR entries that fail the sanity check are pointing
On 12/13/2019 5:52 PM, Lu Baolu wrote:
On 12/13/19 10:31 PM, Barret Rhoden wrote:
On 12/11/19 9:43 PM, Lu Baolu wrote:
The VT-d spec defines the BIOS considerations about RMRR in section
8.4:
"
BIOS must report the RMRR reported memory addresses as reserved (or as
EFI runtime) in the
On 12/11/2019 11:46 AM, Barret Rhoden wrote:
RMRR entries describe memory regions that are DMA targets for devices
outside the kernel's control.
RMRR entries that fail the sanity check are pointing to regions of
memory that the firmware did not tell the kernel are reserved or
otherwise should
On 10/16/2019 12:51 AM, Joerg Roedel wrote:
Hi,
On Tue, Oct 15, 2019 at 09:49:32AM -0700, Yian Chen wrote:
VT-d RMRR (Reserved Memory Region Reporting) regions are reserved
for device use only and should not be part of allocable memory pool of OS.
BIOS e820_table reports complete memory
Hi Barret,
this looks good.
thanks
Yian
On 1/7/2020 11:16 AM, Barret Rhoden wrote:
The VT-d docs specify requirements for the RMRR entries base and end
(called 'Limit' in the docs) addresses.
This commit will cause the DMAR processing to skip any RMRR entries that
do not meet these
On 2/17/2022 6:53 PM, Lu Baolu wrote:
Hi Yian,
On 2/17/22 3:36 AM, Yian Chen wrote:
Starting from Intel VT-d v3.2, Intel platform BIOS can provide
additional SATC table structure. SATC table includes a list of
SoC integrated devices that support ATC (Address translation
cache).
Enabling ATC
