Re: [RFC 3/3] virtio-iommu: future work

On 21/04/17 09:31, Tian, Kevin wrote: >> From: Jean-Philippe Brucker >> Sent: Saturday, April 8, 2017 3:18 AM >> >> Here I propose a few ideas for extensions and optimizations. This is all >> very exploratory, feel free to correct mistakes and suggest more things. >

Re: [Qemu-devel] [RFC PATCH 1/8] iommu: Introduce bind_pasid_table API function

On 28/04/17 10:04, Liu, Yi L wrote: > On Wed, Apr 26, 2017 at 05:56:45PM +0100, Jean-Philippe Brucker wrote: >> Hi Yi, Jacob, >> >> On 26/04/17 11:11, Liu, Yi L wrote: >>> From: Jacob Pan <jacob.jun@linux.intel.com> >>> >>> Virtual IOMMU w

[RFC] virtio-iommu version 0.4

This is the continuation of my proposal for virtio-iommu, the para- virtualized IOMMU. Here is a summary of the changes since last time [1]: * The virtio-iommu document now resembles an actual specification. It is split into a formal description of the virtio device, and implementation notes.

[RFC] virtio-iommu v0.4 - IOMMU Device

The following is roughly the content of device-operations.tex --- \section{IOMMU device}\label{sec:Device Types / IOMMU Device} The virtio-iommu device manages Direct Memory Access (DMA) from one or more endpoints. It may act as a proxy for multiple physical IOMMUs managing devices assigned to

[RFC] virtio-iommu v0.4 - Implementation notes

The following is roughly the content of topology.tex and MSI.tex --- \section{Implementation notes}\label{sec:viommu} \subsection{Virtual system topology}\label{sec:viommu / Virtual topology} \subsubsection{Example virtual topology}\label{sec:viommu / Virtual topology / Example}

Re: Support SVM without PASID

On 01/08/17 18:38, valmiki wrote: [...] >>> So i digged through your patches and i understood that using BIND ioctls >>> satge-1 translations are setup in SMMU for an application. >>> If we use VFIO_IOMMU_MAP/UNMAP_DMA ioctls they are setting up stage-2 >>> translations in SMMU. >>> So without

Re: Support SVM without PASID

On 08/08/17 01:51, Bob Liu wrote: > On 2017/8/7 20:52, Jean-Philippe Brucker wrote: >> Hi Bob, >> >> On 07/08/17 13:18, Bob Liu wrote: >>> On 2017/8/7 18:31, Jean-Philippe Brucker wrote: >>>> On 05/08/17 06:14, valmiki wrote: >>>> [...] >&g

Re: Support SVM without PASID

Hi Bob, On 07/08/17 13:18, Bob Liu wrote: > On 2017/8/7 18:31, Jean-Philippe Brucker wrote: >> On 05/08/17 06:14, valmiki wrote: >> [...] >>> Hi Jean, Thanks a lot, now i understood the flow. From vfio kernel >>> documentation we fill vaddr and iova in struct vfio

Re: [RFC 2/3] virtio-iommu: device probing and operations

On 22/08/17 07:24, Tian, Kevin wrote: >>> (sorry to pick up this old thread, as the .tex one is not good for review >>> and this thread provides necessary background for IOASID). >>> >>> Hi, Jean, >>> >>> I'd like to hear more clarification regarding the relationship between >>> IOASID and PASID.

Re: [RFC] virtio-iommu version 0.4

On 04/08/17 19:19, Jean-Philippe Brucker wrote: > Other extensions are in preparation. I won't detail them here because v0.4 > already is a lot to digest, but in short, building on top of PROBE: > > * First, since the IOMMU is paravirtualized, the device can expose some &g

Re: [RFC PATCH 7/8] VFIO: Add new IOCTL for IOMMU TLB invalidate propagation

Hi Yi, On 26/04/17 11:12, Liu, Yi L wrote: > From: "Liu, Yi L" > > This patch adds VFIO_IOMMU_TLB_INVALIDATE to propagate IOMMU TLB > invalidate request from guest to host. > > In the case of SVM virtualization on VT-d, host IOMMU driver has > no knowledge of caching

Re: [RFC PATCH 7/8] VFIO: Add new IOCTL for IOMMU TLB invalidate propagation

On 14/05/17 11:12, Liu, Yi L wrote: > On Fri, May 12, 2017 at 01:11:02PM +0100, Jean-Philippe Brucker wrote: >> Hi Yi, >> >> On 26/04/17 11:12, Liu, Yi L wrote: >>> From: "Liu, Yi L" <yi.l@linux.intel.com> >>> >>> This patch adds

Re: [PATCH 1/2] PCI: Save properties required to handle FLR for replay purposes.

Hi, On 10/05/17 19:39, Ashok Raj wrote: > From: CQ Tang > > Requires: https://patchwork.kernel.org/patch/9593891 Since your series is likely to go in much earlier than my SVM mess, maybe you could carry that PCI patch along with it? Or I could resend it on its own if you

Re: [RFC PATCH 04/30] iommu/arm-smmu-v3: Add support for PCI ATS

On 10/05/17 13:54, Tomasz Nowicki wrote: > Hi Jean, > > On 27.02.2017 20:54, Jean-Philippe Brucker wrote: >> +/* >> + * Returns -ENOSYS if ATS is not supported either by the device or by >> the SMMU >> + */ >> +static int arm_smmu_enable_ats(struct arm_smmu

Re: [Qemu-devel] [RFC PATCH 5/8] VFIO: Add new IOTCL for PASID Table bind propagation

On 17/05/17 11:27, Liu, Yi L wrote: > On Fri, May 12, 2017 at 03:58:51PM -0600, Alex Williamson wrote: >> On Wed, 26 Apr 2017 18:12:02 +0800 >> "Liu, Yi L" wrote: >>> >>> +/* IOCTL for Shared Virtual Memory Bind */ >>> +struct vfio_device_svm { >>> + __u32 argsz; >>>

Re: [RFC PATCH 07/30] iommu/arm-smmu-v3: Add second level of context descriptor table

On 15/05/17 13:47, Tomasz Nowicki wrote: > Hi Jean, > > On 27.02.2017 20:54, Jean-Philippe Brucker wrote: >> @@ -1213,17 +1356,59 @@ static void arm_smmu_free_cd_tables(struct >> arm_smmu_master_data *master) >> __maybe_unused >> static int arm_smmu_alloc_cd(st

Re: [PATCH 2/7] dt-bindings: PCI: Describe ATS property for root complex nodes

On 06/06/2017 12:11 PM, Jean-Philippe Brucker wrote: > On 05/06/17 18:20, Rob Herring wrote: >> pci-host-{e,}cam-generic is a special case. I'm okay with having a >> property for that I suppose. We should not require this property though >> and allow for it to be implie

Re: [RFC,20/30] iommu/arm-smmu-v3: Enable PCI PASID in masters

On 06/23/2017 03:39 PM, Sinan Kaya wrote: > Hi Jean-Philippe, > >> On 2/27/2017 2:54 PM, Jean-Philippe Brucker wrote: >> Enable PASID for PCI devices that support it. >> >> Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> >>

Re: [RFC PATCH 04/30] iommu/arm-smmu-v3: Add support for PCI ATS

On 23/05/17 09:41, Leizhen (ThunderTown) wrote: > On 2017/2/28 3:54, Jean-Philippe Brucker wrote: >> PCIe devices can implement their own TLB, named Address Translation Cache >> (ATC). Steps involved in the use and maintenance of such caches are: >> >> * Device sends an

[PATCH 0/7] Add PCI ATS support to SMMUv3

hes, * added invalidate-all on domain detach, * removed smmu_group again, * removed invalidation print from the fast path, * disabled tagged pointers for good, * some style changes. These patches are based on Linux v4.12-rc2 [1] https://www.spinics.net/lists/linux-pci/msg58650.html Jean-Philippe Brucker

[PATCH 3/7] iommu/of: Check ATS capability in root complex nodes

The PCI root complex node in DT has a property indicating whether it supports ATS. Store this bit in the IOMMU fwspec when initializing a device, so it can be accessed later by an IOMMU driver. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/of_iommu

[PATCH 1/7] PCI: Move ATS declarations outside of CONFIG_PCI

. Since CONFIG_PCI_ATS is only enabled in association with CONFIG_PCI, move defines outside of CONFIG_PCI to prevent build failure when PCI is disabled. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> Acked-by: Bjorn Helgaas <bhelg...@google.com> --- include/linu

[PATCH 2/7] dt-bindings: PCI: Describe ATS property for root complex nodes

ore likely that the size fields will be invalid and either end will detect the error, but in any case, it is undesirable. Add a way for firmware to tell the OS that ATS is supported by the PCI root complex. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- Document

[PATCH 5/7] iommu/arm-smmu-v3: Link domains and devices

domain, protected by a spinlock. It is updated every time we attach or detach devices to and from domains. It needs to be a spinlock because we'll invalidate ATC entries from within hardirq-safe contexts, but it may be possible to relax the read side with RCU later. Signed-off-by: Jean-Philippe

[PATCH 7/7] iommu/arm-smmu-v3: Disable tagged pointers

Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/arm-smmu-v3.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 87ed6239b9a6..0b2674f8ba0f 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/i

[PATCH 4/7] ACPI/IORT: Check ATS capability in root complex nodes

Root complex node in IORT has a bit telling whether it supports ATS or not. Store this bit in the IOMMU fwspec when setting up a device, so it can be accessed later by an IOMMU driver. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/acpi/arm64/iort.

[PATCH 6/7] iommu/arm-smmu-v3: Add support for PCI ATS

page or block, while ATC invalidations target IOVA ranges. * TLB invalidation by context is performed when freeing the domain, at which point there isn't any device attached anymore. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/arm-smmu-v3.c

Re: [RFC PATCH 05/30] iommu/arm-smmu-v3: Disable tagged pointers when ATS is in use

On 22/05/17 07:27, Leizhen (ThunderTown) wrote: > On 2017/2/28 3:54, Jean-Philippe Brucker wrote: >> The ARM architecture has a "Top Byte Ignore" (TBI) option that makes the >> MMU mask out bits [63:56] of an address, allowing a userspace application >> to store data

Re: [RFC PATCH kvmtool 00/15] Add virtio-iommu

Hi Bharat, On 22/05/17 09:26, Bharat Bhushan wrote: > Hi Jean, > > I am trying to run and review on my side but I see Linux patches are not with > latest kernel version. > Will it be possible for you to share your Linux and kvmtool git repository > reference? Please find linux and kvmtool

Re: [Qemu-devel] [RFC PATCH 1/8] iommu: Introduce bind_pasid_table API function

On 23/05/17 08:50, Liu, Yi L wrote: > On Fri, Apr 28, 2017 at 01:51:42PM +0100, Jean-Philippe Brucker wrote: [...] >>>> >>>> For the next version of my SVM series, I was thinking of passing group >>>> instead of device to iommu_bind. Since all devices in a gr

Re: [PATCH 6/7] iommu/arm-smmu-v3: Add support for PCI ATS

On 30/05/17 11:28, Joerg Roedel wrote: > On Wed, May 24, 2017 at 07:01:42PM +0100, Jean-Philippe Brucker wrote: >> * TLB invalidation by range is batched and committed with a single sync. >> Batching ATC invalidation is inconvenient, endpoints limit the number of >> i

Re: [PATCH 2/7] dt-bindings: PCI: Describe ATS property for root complex nodes

On 30/05/17 11:01, Joerg Roedel wrote: > On Wed, May 24, 2017 at 07:01:38PM +0100, Jean-Philippe Brucker wrote: >> +- ats-supported: if present, the root complex supports the Address >> + Translation Service (ATS). It is able to interpret the AT field in PCIe >> + Tran

Re: [PATCH 2/7] dt-bindings: PCI: Describe ATS property for root complex nodes

On 31/05/17 18:23, Rob Herring wrote: > On Wed, May 24, 2017 at 07:01:38PM +0100, Jean-Philippe Brucker wrote: >> Address Translation Service (ATS) is an extension to PCIe allowing >> endpoints to manage their own IOTLB, called Address Translation Cache >> (ATC). Instead o

Re: [PATCH 0/7] Add PCI ATS support to SMMUv3

On 31/05/17 16:27, Nate Watterson wrote: > Hi Jean-Philippe, > > On 5/24/2017 2:01 PM, Jean-Philippe Brucker wrote: >> PCIe devices can implement their own TLB, named Address Translation Cache >> (ATC). In order to support Address Translation Service (ATS), the >> f

Re: [RFC,20/30] iommu/arm-smmu-v3: Enable PCI PASID in masters

Hi Sinan, On 31/05/17 15:10, Sinan Kaya wrote: > Hi Jean-Philippe, > > On 2/27/2017 2:54 PM, Jean-Philippe Brucker wrote: >> Enable PASID for PCI devices that support it. >> >> Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> >> -

Re: [PATCH 2/7] dt-bindings: PCI: Describe ATS property for root complex nodes

On 05/06/17 18:20, Rob Herring wrote: > On Thu, Jun 01, 2017 at 01:28:01PM +0100, Jean-Philippe Brucker wrote: >> On 31/05/17 18:23, Rob Herring wrote: >>> On Wed, May 24, 2017 at 07:01:38PM +0100, Jean-Philippe Brucker wrote: >>>> Address Translation Service (ATS) is

Re: [virtio-dev] [RFC PATCH linux] iommu: Add virtio-iommu driver

On 16/06/17 09:48, Bharat Bhushan wrote: > Hi Jean >> +static int viommu_map(struct iommu_domain *domain, unsigned long iova, >> + phys_addr_t paddr, size_t size, int prot) { >> +int ret; >> +struct viommu_domain *vdomain = to_viommu_domain(domain); >> +struct

Re: What differences and relations between SVM, HSA, HMM and Unified Memory?

Hello, On 10/06/17 05:06, Wuzongyong (Cordius Wu, Euler Dept) wrote: > Hi, > > Could someone explain differences and relations between the SVM(Shared > Virtual Memory, by Intel), HSA(Heterogeneous System Architecture, by AMD), > HMM(Heterogeneous Memory Management, by Glisse) and UM(Unified

Re: [RFC PATCH 6/6] iommu/arm-smmu-v3: Avoid ILLEGAL setting of STE.S1STALLD and CD.S

On 13/09/17 11:11, Yisheng Xie wrote: > Hi Will, > > On 2017/9/13 11:06, Will Deacon wrote: >> On Tue, Sep 05, 2017 at 01:54:19PM +0100, Jean-Philippe Brucker wrote: >>> On 31/08/17 09:20, Yisheng Xie wrote: >>>> It is ILLEGAL to set STE.S1STALLD if STALL_MO

Re: VFIO on ARM64

On 13/09/17 18:38, valmiki wrote: > On 9/13/2017 6:50 AM, Jean-Philippe Brucker wrote: >> Hi Valmiki, >> >> On 12/09/17 19:01, valmiki wrote: >>> Hi, as per VFIO documentation i see that we need to see >>> "/sys/bus/pci/devices/:06:0d.0/iommu_group&

Re: [RFC] iommu: arm-smmu: stall support

Hi Rob, On 14/09/17 20:44, Rob Clark wrote: > Adds a new domain property for iommu clients to opt-in to stalling > with asynchronous resume, and for the client to determine if the > iommu supports this. > > Current motivation is that: > > a) On 8x96/a530, if we don't enable CFCFG (or HUPCF)

Re: [PATCH] iommu/arm-smmu-v3: Avoid ILLEGAL setting of STE.S1STALLD

On 14/09/17 06:08, Yisheng Xie wrote: > According to Spec, it is ILLEGAL to set STE.S1STALLD if STALL_MODEL > is not 0b00, which means we should not disable stall mode if stall > or terminate mode is not configuable. > > As Jean-Philippe's suggestion, this patch introduce a feature bit >

Re: [RFC] virtio-iommu version 0.4

Hi Eric, On 12/09/17 18:13, Auger Eric wrote: > 2.6.7 > - As I am currently integrating v0.4 in QEMU here are some other comments: > At the moment struct virtio_iommu_req_probe flags is missing in your > header. As such I understood the ACK protocol was not implemented by the > driver in your

Re: [RFC] iommu: arm-smmu: stall support

On 22/09/17 10:02, Joerg Roedel wrote: > On Tue, Sep 19, 2017 at 10:23:43AM -0400, Rob Clark wrote: >> I would like to decide in the IRQ whether or not to queue work or not, >> because when we get a gpu fault, we tend to get 1000's of gpu faults >> all at once (and I really only need to handle the

Re: [PATCH v2] iommu/of: Remove PCI host bridge node check

is effectively redundant, and returning a boolean > value as an int is a bit broken anyway, let's just get rid of it. > > Reported-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> This fixes the 4.14-rc1 issue I had with PCI probing on the FastModel Tested-by: Jean-Philippe

Re: bind pasid table API

Hi Jacob, [Adding Eric as he might need pasid_table_info for vSVM at some point] On 19/09/17 04:45, Jacob Pan wrote: > Hi Jean and All, > > This is a follow-up on the LPC discussion we had last week. > (https://linuxplumbersconf.org/2017/ocw/proposals/4748) > > My understanding is that the

Re: [RFC] virtio-iommu version 0.4

On 20/09/17 10:37, Auger Eric wrote: > Hi Jean, > On 19/09/2017 12:47, Jean-Philippe Brucker wrote: >> Hi Eric, >> >> On 12/09/17 18:13, Auger Eric wrote: >>> 2.6.7 >>> - As I am currently integrating v0.4 in QEMU here are some other comments: >>>

Re: Task based virtual address spaces

Hi Jordan, On 04/10/17 20:43, Jordan Crouse wrote: > Trying to start back up the conversation about multiple address > spaces for IOMMU devices. If you will remember Jean-Philippe posted > some patches back in February for SVM on arm-smmu-v3. > > For quite some time the downstream Snapdragon

[RFCv2 PATCH 35/36] iommu/arm-smmu-v3: Add support for PRI

For PCI devices that support it, enable the PRI capability and handle PRI Page Requests with the generic fault handler. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/arm-smmu-v3.c | 176 ++-- 1 file change

[RFCv2 PATCH 36/36] iommu/arm-smmu-v3: Add support for PCI PASID

Enable PASID for PCI devices that support it. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/arm-smmu-v3.c | 52 + 1 file changed, 52 insertions(+) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iom

[RFCv2 PATCH 08/36] iommu/fault: Handle mm faults

removing the pinning at the moment, though. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/io-pgfault.c | 83 -- 1 file changed, 81 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/io-pgfault.c b/drivers/io

[RFCv2 PATCH 10/36] vfio: Add support for Shared Virtual Memory

and unmapping buffers explicitly in the IOMMU. The process page tables are shared with the IOMMU, and mechanisms such as PCI ATS/PRI may be used to handle faults. VFIO_DEVICE_UNBIND_PROCESS removed a bond identified by a PASID. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- d

[RFCv2 PATCH 07/36] iommu: Add a fault handler

and a status, allowing the driver to complete the fault, for instance by sending a PRG Response in PCI PRI. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/Kconfig | 9 ++ drivers/iommu/Makefile| 1 + drivers/iommu/io-pgfault.c

[RFCv2 PATCH 14/36] iommu/arm-smmu-v3: Add support for Substream IDs

ptor table for now, but as with stream and page tables, an SSID can be split to target multiple levels of tables. In all stream table entries, we set S1DSS=SSID0 mode, which forces all traffic lacking an SSID to be routed to context descriptor 0. Signed-off-by: Jean-Philippe Brucker <jean-phi

[RFCv2 PATCH 11/36] iommu/arm-smmu-v3: Link domains and devices

domain, protected by a spinlock. It is updated every time we attach or detach devices to and from domains. It needs to be a spinlock because we'll invalidate ATC entries from within hardirq-safe contexts, but it may be possible to relax the read side with RCU later. Signed-off-by: Jean-Philippe

[RFCv2 PATCH 19/36] arm64: mm: Pin down ASIDs for sharing contexts with devices

track of the number of references. Add a refcount value in mm_context_t for this purpose. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- arch/arm64/include/asm/mmu.h | 1 + arch/arm64/include/asm/mmu_context.h | 11 - arch/arm64/mm/con

[RFCv2 PATCH 17/36] iommu/arm-smmu-v3: Support broadcast TLB maintenance

(ASID, VA) * TLBI ASIDE1IS(ASID) Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/arm-smmu-v3.c | 19 +-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 27376e

[RFCv2 PATCH 21/36] iommu/arm-smmu-v3: Implement process operations

required invalidations. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/arm-smmu-v3.c | 207 1 file changed, 207 insertions(+) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 71fc3a

[RFCv2 PATCH 15/36] iommu/arm-smmu-v3: Add second level of context descriptor table

The SMMU can support up to 20 bits of SSID. Add a second level of page tables to accommodate this. Devices that support more than 1024 SSIDs now have a table of 1024 L1 entries (8kB), pointing to tables of 1024 context descriptors (64kB), allocated on demand. Signed-off-by: Jean-Philippe Brucker

[RFCv2 PATCH 13/36] iommu/of: Add stall and pasid properties to iommu_fwspec

Add stall and pasid properties to iommu_fwspec, and fill them when dma-can-stall and pasid-bits properties are present in the device tree. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/of_iommu.c | 10 ++ include/linux/iommu.h| 2 ++ 2

[RFCv2 PATCH 20/36] iommu/arm-smmu-v3: Track ASID state

are using it. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/arm-smmu-v3.c | 53 + 1 file changed, 44 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 96347a

[RFCv2 PATCH 29/36] iommu/arm-smmu-v3: Add stall support for platform devices

stall for devices that support it (opt-in by firmware). When an event corresponds to a translation error, call the IOMMU fault handler. If the fault is recoverable, it will call us back to terminate or continue the stall. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.

[RFCv2 PATCH 30/36] ACPI/IORT: Check ATS capability in root complex nodes

firmare descriptions. The SMMU has a feature bit telling if it supports ATS, which might be sufficient in most systems for deciding whether or not we should enable the ATS capability in endpoints. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/acpi/arm64/iort.

[RFCv2 PATCH 31/36] iommu/arm-smmu-v3: Add support for PCI ATS

page or block, while ATC invalidations target IOVA ranges. * TLB invalidation by context is performed when freeing the domain, at which point there isn't any device attached anymore. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/arm-smmu-v3.c

[RFCv2 PATCH 26/36] iommu/arm-smmu-v3: Add support for Hardware Translation Table Update

If the SMMU supports it and the kernel was built with HTTU support, enable hardware update of access and dirty flags. This is essential for shared page tables, to reduce the number of access faults on the fault queue. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.

[RFCv2 PATCH 22/36] iommu/io-pgtable-arm: Factor out ARM LPAE register defines

For SVM, we'll need to extract CPU page table information and mirror it in the substream setup. Move relevant defines to a common header. Fix TCR_SZ_MASK while we're at it. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- MAINTAINERS| 1 + d

[RFCv2 PATCH 16/36] iommu/arm-smmu-v3: Add support for VHE

in the SMMU and for all streams. Normal DMA mappings will need to use TLBI_EL2 commands instead of TLBI_NH, but shouldn't be otherwise affected by this change. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/arm-smmu-v3.c | 29 -

[RFCv2 PATCH 24/36] iommu/arm-smmu-v3: Steal private ASID from a domain

to prevent racing with attach_dev over the foreign domain. We now need to also take this lock when modifying entry 0 of the context table. Concurrent modifications of a given context table used to be prevented by group->mutex but in this patch we modify the CD of another group. Signed-off-by: Jean-Phili

[RFCv2 PATCH 23/36] iommu/arm-smmu-v3: Share process page tables

Copy the content of TCR, MAIR and TTBR of a given task into a context descriptor. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/arm-smmu-v3.c | 38 -- 1 file changed, 36 insertions(+), 2 deletions(-) diff

[RFCv2 PATCH 18/36] iommu/arm-smmu-v3: Add SVM feature checking

Aggregate all sanity-checks for sharing CPU page tables with the SMMU under a single ARM_SMMU_FEAT_SVM bit. For PCIe SVM, users also need to check FEAT_ATS and FEAT_PRI. For platform SVM, they will most likely have to check FEAT_STALLS and FEAT_BTM. Signed-off-by: Jean-Philippe Brucker <j

[RFCv2 PATCH 28/36] iommu/arm-smmu-v3: Maintain a SID->device structure

When handling faults from the event or PRI queue, we need to find the struct device associated to a SID. Add a rb_tree to keep track of SIDs. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/arm-smmu-v3.c | 104 +

[RFCv2 PATCH 33/36] iommu/arm-smmu-v3: Disable tagged pointers

Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/arm-smmu-v3.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index f591f1974228..f008b4617cd4 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/i

[RFCv2 PATCH 32/36] iommu/arm-smmu-v3: Hook ATC invalidation to process ops

The core calls us when a process is modified. Perform the required ATC invalidations. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/arm-smmu-v3.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm-smmu-

[RFCv2 PATCH 34/36] PCI: Make "PRG Response PASID Required" handling common

- PRG Response PASID Required). Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/amd_iommu.c | 19 +-- drivers/pci/ats.c | 17 + include/linux/pci-ats.h | 8 include/uapi/linux/pci_regs.h |

[RFCv2 PATCH 27/36] iommu/arm-smmu-v3: Register fault workqueue

a complete cycle (two batch increments.) Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/arm-smmu-v3.c | 104 +++- 1 file changed, 102 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm-smmu-v3.c b/d

[RFCv2 PATCH 25/36] iommu/arm-smmu-v3: Use shared ASID set

contexts. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/arm-smmu-v3.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index e89e6d1263d9..b7355630526a 100644 --- a/drivers/iom

[RFCv2 PATCH 03/36] iommu/process: Add public function to search for a process

The fault handler will need to find a process given its PASID. This is the reason we have an IDR for storing processes, so hook it up. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/iommu-process.c | 35 +++ include

[RFCv2 PATCH 05/36] iommu/process: Bind and unbind process to and from devices

to iommu_process_bind_device for the same process are not supported at the moment (they'll race on process_alloc which will only succeed for the first one; the others will have to retry the bind). I also don't support calling bind() on a dying process, not sure if it matters. Signed-off-by: Jean-Philippe

[RFCv2 PATCH 01/36] iommu: Keep track of processes and PASIDs

for allocating PASIDs and retrieving contexts. We also use a single spinlock. These can be refined and optimized later (a custom allocator will be needed for top-down PASID allocation). Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/Kconfig | 10 ++ d

[RFCv2 PATCH 00/36] Process management for IOMMU + SVM for SMMUv3

8089/ [3] git://linux-arm.org/linux-jpb svm/rfc2 [4] https://patchwork.kernel.org/patch/9963863/ [5] https://patchwork.kernel.org/patch/9952257/ Jean-Philippe Brucker (36): iommu: Keep track of processes and PASIDs iommu: Add a process_exit callback for device drivers iommu/process: Add publ

[RFCv2 PATCH 02/36] iommu: Add a process_exit callback for device drivers

for IOMMU masters. This can become problematic if different devices in a domain are managed by distinct device drivers (for example multiple devices in the same group). The problem is the same for the fault handler, so we'll probably fix them all at once. Signed-off-by: Jean-Philippe Brucker <j

[RFCv2 PATCH 04/36] iommu/process: Track process changes with an mmu_notifier

device drivers free the process explicitly by calling unbind (or detaching the device). In the other case the process could crash before unbind, in which case the release notifier has to do all the work. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu

[RFCv2 PATCH 06/36] iommu: Extend fault reporting

ction also takes flags as arguments, giving future users a way to specify at which point of the fault process they want to be called. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- drivers/iommu/iommu.c | 42 ++ include/li

[RFCv2 PATCH 12/36] dt-bindings: document stall and PASID properties for IOMMU masters

supports stall and PASID. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- Documentation/devicetree/bindings/iommu/iommu.txt | 24 +++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/iommu.txt b/Documentation/devi

[RFCv2 PATCH 09/36] iommu/fault: Allow blocking fault handlers

both in blocking and non-blocking context, so it can filter faults early and only execute the blocking code for some of them. Add the IOMMU_FAULT_ATOMIC fault flag to tell the driver where we're calling it from. Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> --- Rob,

Re: Task based virtual address spaces

On 05/10/17 11:08, Jean-Philippe Brucker wrote: > but I'll Cc you so we can work something out. D'oh! I knew I would forget some Ccs... Very sorry about that, please find the thread here: https://lists.linuxfoundation.org/pipermail/iommu/2017-October/024502.html Thanks, J

Re: [PATCH v2 01/16] iommu: introduce bind_pasid_table API function

On 06/10/17 00:03, Jacob Pan wrote: > Virtual IOMMU was proposed to support Shared Virtual Memory (SVM) > use in the guest: > https://lists.gnu.org/archive/html/qemu-devel/2016-11/msg05311.html > > As part of the proposed architecture, when an SVM capable PCI > device is assigned to a guest,

Re: [virtio-dev] [RFC] virtio-iommu version 0.4

d of kmalloc. Thanks, Jean --- 8< --- >From 3fc957560e1e6f070a0468bf75ebc4862d37ff82 Mon Sep 17 00:00:00 2001 From: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> Date: Mon, 9 Oct 2017 20:13:57 +0100 Subject: [PATCH] iommu/virtio-iommu: Allocate all requests on the heap When

Re: [PATCH v2 08/16] iommu: introduce device fault data

On 06/10/17 00:03, Jacob Pan wrote: > Device faults detected by IOMMU can be reported outside IOMMU > subsystem. This patch intends to provide a generic device > fault data such that device drivers can communicate IOMMU faults > without model specific knowledge. > > The assumption is that model

Re: [RFCv2 PATCH 12/36] dt-bindings: document stall and PASID properties for IOMMU masters

On 13/10/17 20:10, Rob Herring wrote: > On Fri, Oct 06, 2017 at 02:31:39PM +0100, Jean-Philippe Brucker wrote: >> On ARM systems, some platform devices behind an IOMMU may support stall >> and PASID features. Stall is the ability to recover from page faults and >> PASID of

Re: [PATCH v2 10/16] iommu: introduce device fault report API

Hi Jacob, On 06/10/17 00:03, Jacob Pan wrote: > Traditionally, device specific faults are detected and handled within > their own device drivers. When IOMMU is enabled, faults such as DMA > related transactions are detected by IOMMU. There is no generic > reporting mechanism to report faults back

Re: [PATCH v2 01/16] iommu: introduce bind_pasid_table API function

On 10/10/17 22:42, Jacob Pan wrote: [...] >>> +/** >>> + * PASID table data used to bind guest PASID table to the host >>> IOMMU. This will >>> + * enable guest managed first level page tables. >>> + * @version: for future extensions and identification of the data >>> format >>> + * @bytes: size

Re: [PATCH v2 03/16] iommu: introduce iommu invalidate API function

On 11/10/17 13:15, Joerg Roedel wrote: > On Wed, Oct 11, 2017 at 11:54:52AM +, Liu, Yi L wrote: >> I didn't quite get 'iovm' mean. Can you explain a bit about the idea? > > It's short for IO Virtual Memory, basically a replacement term for 'svm' > that is not ambiguous (afaik) and not

Re: [RFCv2 PATCH 00/36] Process management for IOMMU + SVM for SMMUv3

On 12/10/17 13:05, Yisheng Xie wrote: [...] * An iommu_process can be bound to multiple domains, and a domain can have multiple iommu_process. >>> when bind a task to device, can we create a single domain for it? I am >>> thinking >>> about process management without shared PT(for

Re: [RFCv2 PATCH 05/36] iommu/process: Bind and unbind process to and from devices

please see > below. > > On Fri, Oct 06, 2017 at 02:31:32PM +0100, Jean-Philippe Brucker wrote: >> +int iommu_process_bind_device(struct device *dev, struct task_struct *task, >> + int *pasid, int flags) > > I just took this patch as an example, i

Re: [PATCH v2 03/16] iommu: introduce iommu invalidate API function

On 12/10/17 11:07, Bob Liu wrote: > On 2017/10/12 17:50, Liu, Yi L wrote: >> >> >>> -Original Message- >>> From: Bob Liu [mailto:liub...@huawei.com] >>> Sent: Thursday, October 12, 2017 5:39 PM >>> To: Jean-Philippe Brucker <jean-philip

Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3

On 06/09/17 02:16, Yisheng Xie wrote: > Hi Jean-Philippe, > > On 2017/9/5 20:56, Jean-Philippe Brucker wrote: >> On 31/08/17 09:20, Yisheng Xie wrote: >>> Jean-Philippe has post a patchset for Adding PCIe SVM support to ARM SMMUv3: >>> https://www.spinics.ne

Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3

On 06/09/17 02:02, Bob Liu wrote: > On 2017/9/5 20:56, Jean-Philippe Brucker wrote: >> On 31/08/17 09:20, Yisheng Xie wrote: >>> Jean-Philippe has post a patchset for Adding PCIe SVM support to ARM SMMUv3: >>> https://www.spinics.net/lists/arm-kernel/msg565155.html &g

Re: [virtio-dev] [RFC] virtio-iommu version 0.4

Hi Eric, On 23/08/17 14:55, Auger Eric wrote: > Please find some comments/questions below: Thanks a lot for this. Sorry for the delay, I was on holiday and it took me a while to sort out the details. > 2.6.7:1 > I do not understand the footnode #6 sentence: 'Without a specific > definition of

Re: [RFC] virtio-iommu version 0.4

Hi Kevin, On 28/08/17 08:39, Tian, Kevin wrote: > Here comes some comments: > > 1.1 Motivation > > You describe I/O page faults handling as future work. Seems you considered > only recoverable fault (since "aka. PCI PRI" being used). What about other > unrecoverable faults e.g. what to do if a

<    1   2   3   4   5   6   7   8   9   10   >