From: Jean-Philippe Brucker
When a recoverable page fault is handled by the fault workqueue, find the
associated mm and call handle_mm_fault.
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/io-pgfault.c | 86 +-
1 file changed, 84 insertions(+), 2
From: Jean-Philippe Brucker
The fault handler will need to find an mm given its PASID. This is the
reason we have an IDR for storing address spaces, so hook it up.
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/iommu-sva.c | 19 +++
include/linux/iommu.h | 9
/20200213205600.19690-1-r...@kernel.org/
Jean-Philippe Brucker (5):
PCI/ATS: Export symbols of PASID functions
iommu/arm-smmu-v3: Add support for PCI PASID
iommu/arm-smmu-v3: Write level-1 descriptors atomically
iommu/arm-smmu-v3: Add command queue batching helpers
iommu/arm-smmu-v3: Batch context
Rather than publishing one command at a time when invalidating a context
descriptor, batch the commands for all SIDs in the domain.
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/arm-smmu-v3.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm
Use WRITE_ONCE() to make sure that the SMMU doesn't read incomplete
stream table descriptors. Refer to the comment about 64-bit accesses,
and add the comment to the equivalent context descriptor code.
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/arm-smmu-v3.c | 4 +++-
1 file changed
From: Jean-Philippe Brucker
Aggregate all sanity-checks for sharing CPU page tables with the SMMU
under a single ARM_SMMU_FEAT_SVA bit. For PCIe SVA, users also need to
check FEAT_ATS and FEAT_PRI. For platform SVA, they will most likely have
to check FEAT_STALLS.
Signed-off-by: Jean-Philippe
When a device or driver misbehaves, it is possible to receive events
much faster than we can print them out. Ratelimit the printing of
events.
Signed-off-by: Jean-Philippe Brucker
---
During the SVA tests when the device driver didn't properly stop DMA
before unbinding, the event queue thread
From: Jean-Philippe Brucker
The SMMUv3 can handle invalidation targeted at TLB entries with shared
ASIDs. If the implementation supports broadcast TLB maintenance, enable it
and keep track of it in a feature bit. The SMMU will then be affected by
inner-shareable TLB invalidations from other
From: Jean-Philippe Brucker
On ARM systems, some platform devices behind an IOMMU may support stall,
which is the ability to recover from page faults. Let the firmware tell us
when a device supports stall.
Reviewed-by: Rob Herring
Signed-off-by: Jean-Philippe Brucker
---
.../devicetree
f-by: Jean-Philippe Brucker
---
include/linux/pci-ats.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/linux/pci-ats.h b/include/linux/pci-ats.h
index f75c307f346d..e9e266df9b37 100644
--- a/include/linux/pci-ats.h
+++ b/include/linux/pci-ats.h
@@ -28,6 +28,14 @@ int pci_enable_
From: Jean-Philippe Brucker
The core calls us when an mm is modified. Perform the required ATC
invalidations.
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/arm-smmu-v3.c | 44 -
1 file changed, 38 insertions(+), 6 deletions(-)
diff --git a/drivers
The SMMUv3 driver uses pci_{enable,disable}_pri() and related
functions. Export those functions to allow the driver to be built as a
module.
Cc: Bjorn Helgaas
Signed-off-by: Jean-Philippe Brucker
---
drivers/pci/ats.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/ats.c b
From: Jean-Philippe Brucker
The SMMU provides a Stall model for handling page faults in platform
devices. It is similar to PCI PRI, but doesn't require devices to have
their own translation cache. Instead, faulting transactions are parked and
the OS is given a chance to fix the page tables
From: Jean-Philippe Brucker
For PCI devices that support it, enable the PRI capability and handle PRI
Page Requests with the generic fault handler. It is enabled on demand by
iommu_sva_device_init().
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/arm-smmu-v3.c | 278
From: Jean-Philippe Brucker
When handling faults from the event or PRI queue, we need to find the
struct device associated to a SID. Add a rb_tree to keep track of SIDs.
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/arm-smmu-v3.c | 177 +---
1 file
On Tue, Feb 25, 2020 at 11:10:34AM -0800, Christoph Hellwig wrote:
> On Mon, Feb 24, 2020 at 03:26:37PM -0800, Jacob Pan wrote:
> > This patch is an initial step to replace Intel SVM code with the
> > following IOMMU SVA ops:
> > intel_svm_bind_mm() => iommu_sva_bind_device()
> >
On Thu, Feb 27, 2020 at 05:43:51PM +, Jonathan Cameron wrote:
> On Mon, 24 Feb 2020 19:23:42 +0100
> Jean-Philippe Brucker wrote:
>
> > From: Jean-Philippe Brucker
> >
> > To enable address space sharing with the IOMMU, introduce mm_context_get()
> > an
On Thu, Feb 27, 2020 at 06:17:26PM +, Jonathan Cameron wrote:
> On Mon, 24 Feb 2020 19:23:58 +0100
> Jean-Philippe Brucker wrote:
>
> > From: Jean-Philippe Brucker
> >
> > The SMMU provides a Stall model for handling page faults in platform
> >
On Wed, Feb 26, 2020 at 04:44:53PM +0800, Xu Zaibo wrote:
> Hi,
>
>
> On 2020/2/25 2:23, Jean-Philippe Brucker wrote:
> > From: Jean-Philippe Brucker
> >
> > The SMMU provides a Stall model for handling page faults in platform
> > devices. It is similar to
On Wed, Mar 04, 2020 at 02:37:08PM +0100, Joerg Roedel wrote:
> Hi Michael,
>
> On Tue, Mar 03, 2020 at 11:09:41AM -0500, Michael S. Tsirkin wrote:
> > No. It's coded into the hardware. Which might even be practical
> > for bare-metal (e.g. on-board flash), but is very practical
> > when the
On Mon, Feb 24, 2020 at 10:22:02AM -0800, Raj, Ashok wrote:
> Hi Kenneth,
>
> sorry for waking up late on this patchset.
>
>
> On Wed, Jan 15, 2020 at 10:12:46PM +0800, Zhangfei Gao wrote:
> [... trimmed]
>
> > +
> > +static int uacce_fops_open(struct inode *inode, struct file *filep)
> > +{
>
On Wed, Feb 26, 2020 at 12:35:06PM +, Jonathan Cameron wrote:
> > + * A single Process Address Space ID (PASID) is allocated for each mm. In
> > the
> > + * example, devices use PASID 1 to read/write into address space X and
> > PASID 2
> > + * to read/write into address space Y. Calling
On Fri, Feb 28, 2020 at 10:48:44AM -0400, Jason Gunthorpe wrote:
> On Fri, Feb 28, 2020 at 03:39:35PM +0100, Jean-Philippe Brucker wrote:
> > > > + list_for_each_entry_rcu(bond, _mm->devices, mm_head) {
> > > > + /*
> > > > +
On Wed, Feb 26, 2020 at 01:59:33PM +, Jonathan Cameron wrote:
> > +static int iopf_complete(struct device *dev, struct iopf_fault *iopf,
> > +enum iommu_page_response_code status)
>
> This is called once per group. Should name reflect that?
Ok
[...]
> > +/**
> > + *
On Wed, Feb 26, 2020 at 11:39:59AM -0800, Jacob Pan wrote:
> > @@ -442,11 +444,20 @@ static void iommu_sva_unbind_locked(struct
> > iommu_bond *bond)
> > void iommu_sva_unbind_generic(struct iommu_sva *handle)
> > {
> > + int pasid;
> > struct iommu_param *param =
On Tue, Feb 25, 2020 at 10:08:14AM -0400, Jason Gunthorpe wrote:
> On Tue, Feb 25, 2020 at 10:24:39AM +0100, Jean-Philippe Brucker wrote:
> > On Mon, Feb 24, 2020 at 03:00:56PM -0400, Jason Gunthorpe wrote:
> > > On Mon, Feb 24, 2020 at 07:23:36PM +0100, Jean-Phil
my list to look at
> On Mon, 24 Feb 2020 19:23:37 +0100
> Jean-Philippe Brucker wrote:
>
> > From: Jean-Philippe Brucker
> >
> > Add a small library to help IOMMU drivers manage process address
> > spaces bound to their devices. Register an MMU notifier to track
>
[2] https://jpbrucker.net/git/qemu virtio-iommu/devel
Jean-Philippe Brucker (3):
iommu/virtio: Add topology description to virtio-iommu config space
PCI: Add DMA configuration for virtual platforms
iommu/virtio: Enable x86 support
MAINTAINERS | 2 +
drivers/iom
virtio-iommu implementations. It also
enables an IOMMU for lightweight hypervisors that do not rely on
firmware methods for booting.
Signed-off-by: Eric Auger
Signed-off-by: Jean-Philippe Brucker
---
MAINTAINERS | 2 +
drivers/iommu/Kconfig | 10
Kconfig
to select it.
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index f8cb45d84bb0..87efc48c244e 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
configuration methods.
Signed-off-by: Jean-Philippe Brucker
---
drivers/pci/pci-driver.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index 0454ca0e4e3f..69303a814f21 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
On Fri, Feb 28, 2020 at 11:13:40AM -0400, Jason Gunthorpe wrote:
> On Fri, Feb 28, 2020 at 04:04:27PM +0100, Jean-Philippe Brucker wrote:
> > On Fri, Feb 28, 2020 at 10:48:44AM -0400, Jason Gunthorpe wrote:
> > > On Fri, Feb 28, 2020 at 03:39:35PM +0100, Jean-Phil
On Fri, Mar 06, 2020 at 04:39:37PM +0800, Hanjun Guo wrote:
> Hi Joerg,
>
> On 2020/2/28 23:08, Joerg Roedel wrote:
> > Hi,
> >
> > here is a patch-set to rename iommu_param to dev_iommu and
> > establish it as a struct for generic per-device iommu-data.
> > Also move the iommu_fwspec pointer
On Fri, Mar 06, 2020 at 10:52:45AM -0400, Jason Gunthorpe wrote:
> On Fri, Mar 06, 2020 at 03:35:56PM +0100, Jean-Philippe Brucker wrote:
> > On Fri, Mar 06, 2020 at 09:09:19AM -0400, Jason Gunthorpe wrote:
> > > On Fri, Mar 06, 2020 at 10:56:14AM +0100, Jean-Philippe Brucke
On Fri, Mar 06, 2020 at 09:09:19AM -0400, Jason Gunthorpe wrote:
> On Fri, Mar 06, 2020 at 10:56:14AM +0100, Jean-Philippe Brucker wrote:
> > I tried to keep it simple like that: normally mmu_notifier_get() is called
> > in bind(), and mmu_notifier_put() is called in unbind().
&g
On Mon, Feb 24, 2020 at 03:00:56PM -0400, Jason Gunthorpe wrote:
> On Mon, Feb 24, 2020 at 07:23:36PM +0100, Jean-Philippe Brucker wrote:
> > The new allocation scheme introduced by 2c7933f53f6b ("mm/mmu_notifiers:
> > add a get/put scheme for the registration")
Hi Zaibo,
On Tue, Feb 25, 2020 at 11:30:05AM +0800, Xu Zaibo wrote:
> > +struct iopf_queue *
> > +iopf_queue_alloc(const char *name, iopf_queue_flush_t flush, void *cookie)
> > +{
> > + struct iopf_queue *queue;
> > +
> > + queue = kzalloc(sizeof(*queue), GFP_KERNEL);
> > + if (!queue)
> >
On Mon, Feb 03, 2020 at 02:41:02PM -0800, Jacob Pan wrote:
> Yeah, that would work as well. I just feel IOMMU UAPI is unlikely to get
> updated frequently, should be much less than adding new capabilities.
> I think argsz could be viewed as the version field set by the
> user, minsz is what kernel
On Sat, Feb 15, 2020 at 03:10:47PM -0600, Bjorn Helgaas wrote:
> On Thu, Feb 13, 2020 at 05:50:40PM +0100, Jean-Philippe Brucker wrote:
> > Each vendor has their own way of describing whether a host bridge
> > supports ATS. The Intel and AMD ACPI tables selectively enable or
>
virtio-iommu implementations. It also
enables an IOMMU for lightweight hypervisors that do not rely on
firmware methods for booting.
Signed-off-by: Eric Auger
Signed-off-by: Jean-Philippe Brucker
---
MAINTAINERS | 2 +
drivers/iommu/Kconfig | 10
/20191122105000.800410-1-jean-phili...@linaro.org/
[2] https://jpbrucker.net/git/qemu virtio-iommu/devel
Jean-Philippe Brucker (3):
iommu/virtio: Add topology description to virtio-iommu config space
PCI: Add DMA configuration for virtual platforms
iommu/virtio: Enable x86 support
nstead of
> one-by-one.
>
> As there is only one caller of arm_smmu_atc_inv_master() left, we can
> simplify it and avoid passing in struct arm_smmu_cmdq_ent.
>
> Cc: Jean-Philippe Brucker
> Cc: Will Deacon
> Cc: Robin Murphy
> Cc: Joerg Roedel
> Signed-off-by: Rob Herring
Re
Hi Joerg,
On Wed, Feb 19, 2020 at 12:16:04PM +0100, Joerg Roedel wrote:
> On Fri, Feb 14, 2020 at 05:38:27PM +0100, Jean-Philippe Brucker wrote:
> > From: Jean-Philippe Brucker
> >
> > Now that the infrastructure changes are in place, enable virtio-iommu to
> > b
From: Jean-Philippe Brucker
Now that the infrastructure changes are in place, enable virtio-iommu to
be built as a module. Remove the redundant pci_request_acs() call, since
it's not exported but is already invoked during DMA setup.
Signed-off-by: Jean-Philippe Brucker
---
This conflicts
With the built-in topology description in place, x86 platforms can now
use the virtio-iommu.
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index 068d4e0e3541
On Sun, Feb 16, 2020 at 04:50:33AM -0500, Michael S. Tsirkin wrote:
> On Fri, Feb 14, 2020 at 04:57:11PM +, Robin Murphy wrote:
> > On 14/02/2020 4:04 pm, Jean-Philippe Brucker wrote:
> > > With the built-in topology description in place, x86 platforms can now
> >
On Fri, Feb 14, 2020 at 05:03:16PM +, Robin Murphy wrote:
> On 14/02/2020 4:04 pm, Jean-Philippe Brucker wrote:
> > Hardware platforms usually describe the IOMMU topology using either
> > device-tree pointers or vendor-specific ACPI tables. For virtual
> > platfor
On Thu, Feb 13, 2020 at 12:26:46PM -0600, Rob Herring wrote:
> On Thu, Feb 13, 2020 at 10:52 AM Jean-Philippe Brucker
> wrote:
> >
> > Copy the ats-supported flag into the pci_host_bridge structure.
> >
> > Signed-off-by: Jean-Philippe Brucker
> > ---
Hi Will,
On Thu, Dec 19, 2019 at 05:30:20PM +0100, Jean-Philippe Brucker wrote:
> Add support for Substream ID and PASIDs to the SMMUv3 driver. Since v3
> [1], I added review and tested tags where appropriate and applied the
> suggested changes, shown in the diff below. Thanks all!
On Tue, Jan 14, 2020 at 12:45:42PM +, Will Deacon wrote:
> On Thu, Dec 19, 2019 at 05:30:33PM +0100, Jean-Philippe Brucker wrote:
> > Enable PASID for PCI devices that support it. Since the SSID tables are
> > allocated by arm_smmu_attach_dev(), PASID has to be enabl
On Tue, Jan 14, 2020 at 03:04:36PM +, Will Deacon wrote:
> On Thu, Dec 19, 2019 at 05:30:30PM +0100, Jean-Philippe Brucker wrote:
> > The SMMU can support up to 20 bits of SSID. Add a second level of page
> > tables to accommodate this. Devices that support more than 1024 SSI
size
is less of a concern, since the PCIe specification "highly recommends"
that devices supporting PASID implement all 20 bits of it.
Tested-by: Zhangfei Gao
Reviewed-by: Eric Auger
Reviewed-by: Jonathan Cameron
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/arm-smmu
should be good to go, but anything in between
would be good too, and I'll send the rest for 5.7.
Thanks,
Jean
[1]
https://lore.kernel.org/linux-iommu/20191219163033.2608177-1-jean-phili...@linaro.org/
Jean-Philippe Brucker (13):
iommu/arm-smmu-v3: Drop __GFP_ZERO flag from DMA allocation
dt
When adding SSID support to the SMMUv3 driver, we'll need to manipulate
leaf pasid tables and context descriptors. Extract the context
descriptor structure and align with the way stream tables are handled.
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/arm-smmu-v3.c | 46
The SMMU can support up to 20 bits of SSID. Add a second level of page
tables to accommodate this. Devices that support more than 1024 SSIDs now
have a table of 1024 L1 entries (8kB), pointing to tables of 1024 context
descriptors (64kB), allocated on demand.
Signed-off-by: Jean-Philippe Brucker
Reviewed-by: Eric Auger
Reviewed-by: Jonathan Cameron
Signed-off-by: Jean-Philippe Brucker
---
include/linux/pci-ats.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/linux/pci-ats.h b/include/linux/pci-ats.h
index 5d62e78946a3..d08f0869f121 100644
--- a/include/linux/pci-ats.h
+++
Enable PASID for PCI devices that support it. Initialize PASID early in
add_device() because it must be enabled before ATS.
Tested-by: Zhangfei Gao
Reviewed-by: Jonathan Cameron
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/arm-smmu-v3.c | 62 -
1
Support for SSID will require allocating context descriptor tables. Move
the context descriptor allocation to separate functions.
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/arm-smmu-v3.c | 47 +++--
1 file changed, 34 insertions(+), 13 deletions
th stream and page tables, an SSID can
be split to index multiple levels of tables.
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/arm-smmu-v3.c | 135 ++--
1 file changed, 112 insertions(+), 23 deletions(-)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/i
vert
DMA buffer allocations to the managed API"), since the managed API
didn't provide a dmam_zalloc_coherent() function.
Reviewed-by: Eric Auger
Reviewed-by: Jonathan Cameron
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/arm-smmu-v3.c | 9 -
1 file changed, 4 insertions(+),
ean-Philippe Brucker
---
drivers/iommu/arm-smmu-v3.c | 13 +
drivers/iommu/of_iommu.c| 6 +-
include/linux/iommu.h | 2 ++
3 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index d4e8b7f8d
the hassle since they are managed resources.
Reviewed-by: Eric Auger
Reviewed-by: Jonathan Cameron
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/arm-smmu-v3.c | 28 +---
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/drivers/iommu/arm-smmu-v3.c b
Second-level context descriptor tables will be allocated lazily in
arm_smmu_write_ctx_desc(). Help with handling allocation failure by
moving the CD write into arm_smmu_domain_finalise_s1().
Reviewed-by: Eric Auger
Reviewed-by: Jonathan Cameron
Signed-off-by: Jean-Philippe Brucker
---
drivers
-off-by: Jean-Philippe Brucker
---
drivers/acpi/arm64/iort.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
index 33f71983e001..39f389214ecf 100644
--- a/drivers/acpi/arm64/iort.c
+++ b/drivers/acpi/arm64/iort.c
@@ -11,6
On Arm systems, some platform devices behind an SMMU may support the PASID
feature, which offers multiple address space. Let the firmware tell us
when a device supports PASID.
Reviewed-by: Eric Auger
Reviewed-by: Jonathan Cameron
Reviewed-by: Rob Herring
Signed-off-by: Jean-Philippe Brucker
On Wed, Jan 15, 2020 at 04:42:56PM +, Will Deacon wrote:
> On Wed, Jan 15, 2020 at 01:52:26PM +0100, Jean-Philippe Brucker wrote:
> > Since v4 [1] I addressed some of Will's comment.
>
> Thanks! I've tentatively managed to queue all of this apart from the last
> patch,
On Tue, Jan 14, 2020 at 12:38:19PM +, Will Deacon wrote:
> > +static void arm_smmu_sync_cd(struct arm_smmu_domain *smmu_domain,
> > +int ssid, bool leaf)
> > +{
> > + size_t i;
> > + unsigned long flags;
> > + struct arm_smmu_master *master;
> > + struct
On Tue, Jan 14, 2020 at 12:42:47PM +, Will Deacon wrote:
> On Thu, Dec 19, 2019 at 05:30:29PM +0100, Jean-Philippe Brucker wrote:
> > Second-level context descriptor tables will be allocated lazily in
> > arm_smmu_write_ctx_desc(). Help with handling allocation failure by
&g
nstead of
> one-by-one.
>
> Cc: Jean-Philippe Brucker
> Cc: Will Deacon
> Cc: Robin Murphy
> Cc: Joerg Roedel
> Signed-off-by: Rob Herring
> ---
> drivers/iommu/arm-smmu-v3.c | 23 +++
> 1 file changed, 19 insertions(+), 4 deletions(-)
>
> di
On Tue, Jan 14, 2020 at 11:06:52AM +, Will Deacon wrote:
> > /* Context descriptor manipulation functions */
> > +static int arm_smmu_alloc_cd_leaf_table(struct arm_smmu_device *smmu,
> > + struct arm_smmu_cd_table *table,
> > +
On Thu, Jan 09, 2020 at 02:41:01PM +, Will Deacon wrote:
> On Thu, Jan 09, 2020 at 03:36:18PM +0100, Jean-Philippe Brucker wrote:
> > On Thu, Dec 19, 2019 at 05:30:20PM +0100, Jean-Philippe Brucker wrote:
> > > Add support for Substream ID and PASIDs to the SMMUv3 driver. Sin
Hi Baolu,
On Thu, Mar 12, 2020 at 09:44:16AM +0800, Lu Baolu wrote:
> Hi Jean,
>
> On 2020/3/11 20:45, Jean-Philippe Brucker wrote:
> > The pci_ats_supported() function checks if a device supports ATS and is
> > allowed to use it.
> >
> > Sig
When initializing a PCI root bridge, copy its "ATS supported" attribute
into the root bridge.
Acked-by: Hanjun Guo
Signed-off-by: Jean-Philippe Brucker
---
drivers/acpi/arm64/iort.c | 27 +++
drivers/acpi/pci_root.c | 3 +++
include/linux/acpi_iort.h | 8 +
is trusted. Devices plugged into external-facing
ports such as thunderbolt are untrusted.
* whether the host bridge supports ATS, which defaults to true unless
the firmware description states that ATS isn't supported by the host
bridge.
Signed-off-by: Jean-Philippe Brucker
---
drivers/pci
.
Signed-off-by: Jean-Philippe Brucker
---
v1->v2: try to improve the comment
---
drivers/pci/probe.c | 8
include/linux/pci.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 512cb4312ddd..b5e36f06b40a 100644
--- a/drivers/pci/prob
* Arm SMMUv3 on patch 7
* Intel VT-d on patch 8
* arm64 DT on patch 10
Thanks,
Jean
[1]
https://lore.kernel.org/linux-iommu/20200213165049.508908-1-jean-phili...@linaro.org/
Jean-Philippe Brucker (11):
dt-bindings: PCI: generic: Add ats-supported property
PCI: Add ats_supported host bridge
The "pci=noats" kernel parameter disables PCIe ATS globally, and affects
any ATS-capable IOMMU driver. So rather than adding Arm SMMUv3, which
recently gained ATS support, to the list of relevant build options,
simplify the noats description.
Signed-off-by: Jean-Philip
Declare that the host controller supports ATS, so the OS can enable it
for ATS-capable PCIe endpoints.
Signed-off-by: Jean-Philippe Brucker
---
arch/arm64/boot/dts/arm/fvp-base-revc.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts
b/arch/arm64
-generic for the moment. For non-generic root controllers,
availability of ATS can be inferred from the compatible string.
Reviewed-by: Rob Herring
Signed-off-by: Jean-Philippe Brucker
---
Documentation/devicetree/bindings/pci/host-generic-pci.yaml | 6 ++
1 file changed, 6 insertions(+)
diff
When setting up a generic host on a device-tree based system, copy the
ats-supported flag into the pci_host_bridge structure.
Signed-off-by: Jean-Philippe Brucker
---
v1->v2: keep the helper in pci-host-common.c
---
drivers/pci/controller/pci-host-common.c | 11 +++
1 file changed,
such as thunderbolt).
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/amd_iommu.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
index aac132bd1ef0..084f0b2e132e 100644
--- a/drivers/iommu/amd_iommu.c
The pci_ats_supported() function checks if a device supports ATS and is
allowed to use it.
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/intel-iommu.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
Now that the ats_supported flag is in the host bridge structure where it
belongs, we can remove it from the per-device fwspec structure.
Acked-by: Hanjun Guo
Signed-off-by: Jean-Philippe Brucker
---
drivers/acpi/arm64/iort.c | 11 ---
include/linux/iommu.h | 4
2 files
The new pci_ats_supported() function checks if a device supports ATS and
is allowed to use it.
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/arm-smmu-v3.c | 18 +++---
1 file changed, 3 insertions(+), 15 deletions(-)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu
though we change the UAPI this shouldn't cause any regression since
QEMU, the existing implementation of virtio-iommu that uses this header,
already removes the annotations when importing headers.
Reported-by: kbuild test robot
Signed-off-by: Jean-Philippe Brucker
---
include/uapi/linux
On Thu, Mar 05, 2020 at 08:07:32AM +, Tian, Kevin wrote:
> > From: Jean-Philippe Brucker
> > Sent: Saturday, February 29, 2020 1:26 AM
> >
> > Platforms without device-tree do not currently have a method for
> > describing the vIOMMU topology. Provide a
2 removes it from the IOMMU API.
Jean-Philippe Brucker (2):
uacce: Remove mm_exit() op
iommu: Remove iommu_sva_ops::mm_exit()
include/linux/iommu.h | 30 ---
include/linux/uacce.h | 34 ++--
drivers/iommu/iommu.c | 11 ---
drivers/misc/uacce/uacce.c | 171
...@ziepe.ca/
[2]
https://lore.kernel.org/linux-iommu/4d68da96-0ad5-b412-5987-2f7a6aa79...@amd.com/
Signed-off-by: Jean-Philippe Brucker
---
include/linux/iommu.h | 30 --
drivers/iommu/iommu.c | 11 ---
2 files changed, 41 deletions(-)
diff --git a/include/linux
all queues bound to an mm, was only
used by the mm_exit() callback. Remove it.
Signed-off-by: Jean-Philippe Brucker
---
include/linux/uacce.h | 34 ++--
drivers/misc/uacce/uacce.c | 171 +
2 files changed, 50 insertions(+), 155 deletions(-)
diff
wrote:
> > > > > Hi Jean,
> > > > >
> > > > > On Wed, 8 Apr 2020 16:04:25 +0200
> > > > > Jean-Philippe Brucker wrote:
> > > > >
> > > > > > The IOMMU SVA API currently requires device drivers to
> > > >
On Wed, Apr 08, 2020 at 12:27:58PM +0200, Auger Eric wrote:
> Hi Yi,
>
> On 4/7/20 11:43 AM, Liu, Yi L wrote:
> > Hi Jean,
> >
> >> From: Jean-Philippe Brucker
> >> Sent: Friday, April 3, 2020 4:23 PM
> >> To: Auger Eric
> >> userspace
On Wed, Apr 08, 2020 at 10:19:40AM -0600, Alex Williamson wrote:
> On Tue, 7 Apr 2020 21:00:21 -0700
> "Raj, Ashok" wrote:
>
> > Hi Alex
> >
> > + Bjorn
>
> + Don
>
> > FWIW I can't understand why PCI SIG went different ways with ATS,
> > where its enumerated on PF and VF. But for PASID and
On Tue, Apr 07, 2020 at 10:33:25AM +, Liu, Yi L wrote:
> Hi Jean,
>
> > From: Jean-Philippe Brucker < jean-phili...@linaro.org >
> > Sent: Friday, April 3, 2020 4:35 PM
> > Subject: Re: [PATCH v1 6/8] vfio/type1: Bind guest page tables to host
> >
> >
On Thu, Apr 09, 2020 at 05:07:34PM +0800, Zhangfei Gao wrote:
>
>
> On 2020/4/8 下午10:04, Jean-Philippe Brucker wrote:
> > The mm_exit() op will be removed from the SVA API. When a process dies
> > and its mm goes away, the IOMMU driver won't notify device drivers
> &
On Thu, Apr 09, 2020 at 09:15:29AM +, Liu, Yi L wrote:
> > From: Jean-Philippe Brucker
> > Sent: Thursday, April 9, 2020 4:29 PM
> > To: Liu, Yi L
> >
> > On Tue, Apr 07, 2020 at 10:33:25AM +, Liu, Yi L wrote:
> > > Hi Jean,
> > >
On Fri, Apr 10, 2020 at 08:52:49AM -0700, Jacob Pan wrote:
> On Thu, 9 Apr 2020 16:50:58 +0200
> Jean-Philippe Brucker wrote:
>
> > > So unbind is coming anyway, the difference in handling in mmu
> > > release notifier is whether we silently drop DMA faul
On Mon, Apr 06, 2020 at 01:02:45PM -0700, Jacob Pan wrote:
> > > + sdata = kzalloc(sizeof(*sdata), GFP_KERNEL);
> > > + if (!sdata)
> > > + return -ENOMEM;
> >
> > I don't understand why we need this structure at all, nor why we need
> > the SID. Users have already allocated an
On Mon, Apr 06, 2020 at 08:33:53AM -0700, Jacob Pan wrote:
> Hi Jean,
>
> On Wed, 1 Apr 2020 15:53:16 +0200
> Jean-Philippe Brucker wrote:
>
> > On Wed, Mar 25, 2020 at 10:55:26AM -0700, Jacob Pan wrote:
> > > Bare metal SVA allocates IOASIDs for native proces
loose some sanity-checking of the memory map provided by
firmware, which doesn't seem catastrophic.
Signed-off-by: Jean-Philippe Brucker
---
So this is the simplest solution, and I don't think we're missing much
by skipping the resource reservation. I've also been exploring a more
complex approach
On Thu, Apr 16, 2020 at 01:58:29PM -0700, Jacob Pan wrote:
> On Wed, 15 Apr 2020 09:47:36 +0200
> Jean-Philippe Brucker wrote:
>
> > On Fri, Apr 10, 2020 at 08:52:49AM -0700, Jacob Pan wrote:
> > > On Thu, 9 Apr 2020 16:50:58 +0200
> > > Jean-Philippe Brucker wr
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