On Tue, Dec 06, 2016 at 06:30:21PM -0500, Rob Clark wrote:
> On Thu, Aug 18, 2016 at 9:05 AM, Will Deacon wrote:
> > Enabling stalling faults can result in hardware deadlock on poorly
> > designed systems, particularly those with a PCI root complex upstream of
> > the SMMU.
>
On Tue, Jan 03, 2017 at 04:30:55PM -0500, Rob Clark wrote:
> At least on the db820c I have, with the firmware I have, I'm not seeing
> the SS bit set, even though the iommu is in a stalled state. So for
> this implementation ignore not having SS bit set.
The SS bit gets set if SCTLR.CFCFG is set
On Thu, Oct 05, 2017 at 11:08:12AM +0100, Jean-Philippe Brucker wrote:
> Hi Jordan,
>
> On 04/10/17 20:43, Jordan Crouse wrote:
> > Trying to start back up the conversation about multiple address
> > spaces for IOMMU devices. If you will remember Jean-Philippe posted
On Thu, Oct 12, 2017 at 01:55:32PM +0100, Jean-Philippe Brucker wrote:
> On 12/10/17 13:05, Yisheng Xie wrote:
> [...]
> * An iommu_process can be bound to multiple domains, and a domain can
> have
> multiple iommu_process.
> >>> when bind a task to device, can we create a single
/TTBR1 virtual address range of 36
bits the memory map will look like this:
TTBR0 [0x:0x0007]
TTBR1 [0xFFF8:0x]
The map/unmap operations will automatically use the appropriate
pagetable for the given iova.
Signed-off-by: Jordan Crouse
The result of iommu_group_get() was being blindly used in both
attach and detach which results in a dereference when trying
to work with an unknown device.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/iommu/iommu.c | 5 +
1 file changed, 5 insertions(+)
diff
On Mon, Oct 23, 2017 at 02:00:07PM +0100, Jean-Philippe Brucker wrote:
> Hi Jordan,
>
> [Lots of IOMMU people have been dropped from Cc, I've tried to add them back]
>
> On 12/10/17 16:28, Jordan Crouse wrote:
> > On Thu, Oct 12, 2017 at 01:55:32PM +0100, Jean-Philippe Bruc
On Wed, Oct 25, 2017 at 02:20:15PM -0600, Jordan Crouse wrote:
> On Mon, Oct 23, 2017 at 02:00:07PM +0100, Jean-Philippe Brucker wrote:
> > Hi Jordan,
> >
> > [Lots of IOMMU people have been dropped from Cc, I've tried to add them
> > back]
> >
> >
On Tue, Feb 13, 2018 at 06:10:38PM +0900, Tomasz Figa wrote:
> Hi Vivek,
>
> Thanks for the patch. Please see my comments inline.
>
> On Wed, Feb 7, 2018 at 7:31 PM, Vivek Gautam
> wrote:
> > While handling the concerned iommu, there should not be a
> > need to
On Wed, Feb 14, 2018 at 12:31:29PM +0900, Tomasz Figa wrote:
> Hi Jordan,
>
> On Wed, Feb 14, 2018 at 1:42 AM, Jordan Crouse <jcro...@codeaurora.org> wrote:
> > On Tue, Feb 13, 2018 at 06:10:38PM +0900, Tomasz Figa wrote:
> >> Hi Vivek,
> >>
> >&
/unmap operations will automatically use the appropriate
pagetable based on the specified iova and the existing mask.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/iommu/arm-smmu-regs.h | 2 -
drivers/iommu/arm-smmu.c | 22 --
drivers/iommu/io-pgtable-arm.c
Add support for allocating and populating pagetables
indexed by pasid. Each new pasid is allocated a pagetable
with the same parameters and format as the parent domain.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/iommu/arm-smmu.c
t that bikeshed if you feel so inclined. Thanks for reading this
far. On with the code.
Applies against git://linux-arm.org/linux-jpb.git sva/v1
Jordan Crouse (14):
iommu: Add DOMAIN_ATTR_ENABLE_TTBR1
iommu/arm-smmu: Add support for TTBR1
iommu: Create a base struct for io_mm
iommu: sva: Ad
In order to support both shared mm sva pagetables as well as
io-pgtable backed tables add a base structure to
io_mm so that the two styles can share the same idr.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/iommu/arm-smmu-v3.c | 8
drivers/iommu/iommu-sva.c
safely.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
include/linux/iommu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 641aaf0f1b81..e2c49e583d8d 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -153,6
Add a function to allocate a new pasid from a existing
MMU domain and create a per-instance address space.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/msm_drv.h | 3 +++
drivers/gpu/drm/msm/msm_gem_vma.c | 36 +++-
2
a msm_mmu struct to abstract (most) of the details
from the rest of the system.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/msm_iommu.c | 184
drivers/gpu/drm/msm/msm_mmu.h | 6 ++
2 files changed, 190 inse
.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 55 ++
drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 17 +++
drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 76 +--
drivers/gpu/drm/msm/
CPU pagetables these implementations
need to a new pagetable structure and populate it manually. Add a
new set of API functions to create and populate a pagetable structure
identified by a pasid.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/iommu/iommu-sva.c
Pass the index of the MMU domain in struct msm_file_private instead
of assuming gpu->id throughout the submit path. This clears the way
to change ctx->aspace to a per-instance pagetable.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/msm_drv.c
Add a few simple support functions to support a bitmask of
features that a specific MMU implementation supports. The
first feature will be per-instance pagetables coming in the
following patch.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/msm_mmu.
Create a per-instance address spaces when a new DRM file instance is
opened assuming the target supports it and the underlying
infrastructure exists. If the operation is unsupported fall back
quietly to use the global pagetable.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
d
pagetables
still need additional support to be enabled but even if they
aren't set up it isn't harmful to just use TTBR1 for all
virtual memory regions and leave the other pagetable unused.
If TTBR1 support isn't enabled then fall back to the "legacy"
virtual address space both kernel and user.
Si
pagetable information to the
client driver whenever a new pasid is created or destroyed
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/iommu/arm-smmu.c | 40
include/linux/arm-smmu.h | 18 ++
2 files changed, 58 inse
addresses so switch over now to prepare for
using addresses above 4G for targets that support them.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 14 ++
drivers/gpu/drm/msm/msm_iommu.c | 2 +-
2 files changed, 15 inse
On Wed, Feb 07, 2018 at 04:01:19PM +0530, Vivek Gautam wrote:
> From: Sricharan R
>
> The smmu device probe/remove and add/remove master device callbacks
> gets called when the smmu is not linked to its master, that is without
> the context of the master device. So
On Fri, Feb 23, 2018 at 04:06:39PM +0530, Vivek Gautam wrote:
> On Fri, Feb 23, 2018 at 5:22 AM, Jordan Crouse <jcro...@codeaurora.org> wrote:
> > On Wed, Feb 07, 2018 at 04:01:19PM +0530, Vivek Gautam wrote:
> >> From: Sricharan R <sricha...@codeaurora.org>
> >
I am very much in the market for better ideas.
[1] https://patchwork.freedesktop.org/series/38729/
Jordan Crouse (2):
iommu: Gracefully allow drivers to not attach to a default domain
iommu/arm-smmu: Add list of devices to opt out of DMA domains
drivers/iommu/arm-smmu.c | 23 +
ork and the next domain to try
to attach will take group->domain for itself and everything will
proceed as normal.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/iommu/iommu.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/d
DMA ops. Later
the client device in question can set up and attach their own
domain.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/iommu/arm-smmu.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-
On Wed, Apr 25, 2018 at 12:10:47PM +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> Depending on the kernel configuration, early ARM architecture setup code
> may have attached the GPU to a DMA/IOMMU mapping that transparently uses
> the IOMMU to back the DMA API.
On Fri, Mar 02, 2018 at 12:25:48PM +, Jean-Philippe Brucker wrote:
> Hi Jordan,
>
> Thank you for this, SMMUv3 and virtio-iommu need these SVA patches as well.
>
> On 21/02/18 22:59, Jordan Crouse wrote:
> [...]> diff --git a/include/linux/iommu.h b/include/li
On Fri, Mar 02, 2018 at 12:27:58PM +, Jean-Philippe Brucker wrote:
> On 21/02/18 22:59, Jordan Crouse wrote:
> [...]
> > +int iommu_sva_alloc_pasid(struct iommu_domain *domain, struct device *dev)
> > +{
> > + int ret, pasid;
> > + struct io_pasid *io_pasid;
On Fri, Mar 02, 2018 at 05:57:21PM +, Robin Murphy wrote:
> On 21/02/18 22:59, Jordan Crouse wrote:
> >Allow a SMMU device to opt into allocating a TTBR1 pagetable.
> >
> >The size of the TTBR1 region will be the same as
> >the TTBR0 size with the sign extension bi
be bound to
> multiple devices. The mm_alloc() IOMMU op must now check if the mm
> argument is NULL, in which case it should allocate io_pgtables instead of
> binding to an mm.
>
> Signed-off-by: Jordan Crouse
> Signed-off-by: Jean-Philippe Brucker
> ---
> Sadly this
On Wed, Oct 17, 2018 at 03:21:43PM +0100, Jean-Philippe Brucker wrote:
> Hi Jordan,
>
> On 12/10/2018 15:32, Jordan Crouse wrote:
> > On Thu, Sep 20, 2018 at 06:00:46PM +0100, Jean-Philippe Brucker wrote:
> >> Provide an API for allocating PASIDs and populating them manual
On Mon, Oct 22, 2018 at 12:50:56PM +0100, Robin Murphy wrote:
> On 22/10/2018 07:53, Tian, Kevin wrote:
> >>From: Jean-Philippe Brucker [mailto:jean-philippe.bruc...@arm.com]
> >>Sent: Saturday, October 20, 2018 2:12 AM
> >>
> >>This is a first prototype adding auxiliary domain support to Arm
On Fri, Oct 19, 2018 at 07:11:52PM +0100, Jean-Philippe Brucker wrote:
> (2) Allocate a domain and attach it to the device.
>
> dom = iommu_domain_alloc()
> iommu_attach_device(dom, dev)
>
> I still have concerns about this part, which are highlighted by the
> messy changes
On Tue, Jul 24, 2018 at 03:13:37PM +0530, Vivek Gautam wrote:
> Hi Will,
>
>
> On Wed, Jun 27, 2018 at 10:07 PM, Will Deacon wrote:
> > Hi Vivek,
> >
> > On Tue, Jun 19, 2018 at 02:04:44PM +0530, Vivek Gautam wrote:
> >> On Fri, Jun 15, 2018 at 10:22 PM, Will Deacon wrote:
> >> > On Fri, Jun
On Mon, Nov 26, 2018 at 07:31:48PM +, Will Deacon wrote:
> Hi Rob,
>
> On Tue, Nov 13, 2018 at 08:12:35AM -0500, Rob Clark wrote:
> > On Tue, Nov 13, 2018 at 1:32 AM Will Deacon wrote:
> > > On Fri, Nov 09, 2018 at 01:01:55PM -0500, Rob Clark wrote:
> > > > On Mon, Oct 29, 2018 at 3:09 PM
> It shouldn't be a problem to hook something else up to the IOMMU
> subsystem. Hopefully it's something that people are going to standardize
> on.
>
> > 3) The automatic attach of DMA domain is also causing a different
> >problem for us on the GPU side, preventing us from supporting per-
> >
-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 5e54cc0..7537639 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -1235,6 +1235,35
.
Jordan Crouse (16):
iommu/arm-smmu: Allow client devices to select direct mapping
iommu: Add DOMAIN_ATTR_SPLIT_TABLES
iommu/io-pgtable-arm: Add support for AARCH64 split pagetables
iommu/arm-smmu: Add support for DOMAIN_ATTR_SPLIT_TABLES
iommu: Add DOMAIN_ATTR_PTBASE
iommu/arm-smmu: Add
that the correct
pagetable is selected based on the incoming iova but most of the
heavy lifting is common.
v3: New patch taking most of the TTBR1 specific code out of arm-smmu
Signed-off-by: Jordan Crouse
---
drivers/iommu/io-pgtable-arm.c | 261 +
drivers
Add a new domain attribute to enable split pagetable support for devices
devices that support it.
Signed-off-by: Jordan Crouse
---
include/linux/iommu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index a815cf6..a2f07cf 100644
--- a/include
If DOMAIN_ATTR_SPLIT_TABLES is specified for a domain pass
ARM_64_LPAE_SPLIT_S1 to io_pgtable_ops to allocate and
initialize TTBR0 and TTBR1 pagetables.
v3: Moved all the pagetable specific work into io-pgtable-arm
in previous patch
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c
addresses in the pagetable. The driver/hardware is used
to switch the pagetable according to its own specific implementation.
v3: Trivial update to reflect new pgtable ops situation
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 125 +--
1
Add an attribute to return the base address of the pagetable. This is used
by auxiliary domains from arm-smmu to return the address of the pagetable
to the leaf driver so that it can set the appropriate pagetable through
it's own means.
Signed-off-by: Jordan Crouse
---
include/linux/iommu.h
On Tue, May 21, 2019 at 07:18:32PM +0100, Robin Murphy wrote:
> On 21/05/2019 17:13, Jordan Crouse wrote:
> >Add support for a split pagetable (TTBR0/TTBR1) scheme for arm-smmu-v2.
> >If split pagetables are enabled, create a pagetable for TTBR1 and set
> >up the sign exte
Add support for a split pagetable (TTBR0/TTBR1) scheme for arm-smmu-v2.
If split pagetables are enabled, create a pagetable for TTBR1 and set
up the sign extension bit so that all IOVAs with that bit set are mapped
and translated from the TTBR1 pagetable.
Signed-off-by: Jordan Crouse
Add a new domain attribute to enable split pagetable support for devices
devices that support it.
Signed-off-by: Jordan Crouse
---
include/linux/iommu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 4ef8bd5..204acd8 100644
--- a/include
addresses in the pagetable. The driver/hardware is used
to switch the pagetable according to its own specific implementation.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 133 +--
1 file changed, 117 insertions(+), 16 deletions(-)
diff --git
Add an attribute to return the base address of the pagetable. This is used
by auxiliary domains from arm-smmu to return the address of the pagetable
to the leaf driver so that it can set the appropriate pagetable through
it's own means.
Signed-off-by: Jordan Crouse
---
include/linux/iommu.h
domain of its own.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 42 ++
drivers/iommu/iommu.c| 29 +++--
include/linux/iommu.h| 3 +++
3 files changed, 68 insertions(+), 6 deletions(-)
diff --git a/drivers
and
drm/msm: Add support to create target specific address spaces
can be merged to the msm-next tree without dependencies on the IOMMU changes.
Only the last three patches will require coordination between the two areas.
Jordan Crouse (15):
iommu/arm-smmu: Allow IOMMU enabled devices to skip DMA
On Tue, May 21, 2019 at 06:43:34PM +0100, Robin Murphy wrote:
> On 21/05/2019 17:13, Jordan Crouse wrote:
> >Allow IOMMU enabled devices specified on an opt-in list to create a
> >default identity domain for a new IOMMU group and bypass the DMA
> >domain created by the IO
On Wed, Jul 10, 2019 at 05:45:37PM +0100, Robin Murphy wrote:
> Hi Jordan,
>
> On 08/07/2019 20:00, Jordan Crouse wrote:
> >Add a new sub-format ARM_64_LPAE_SPLIT_S1 to create and set up split
> >pagetables (TTBR0 and TTBR1). The initialization function sets up the
> &
pagetable is selected based on the incoming iova but
most of the heavy lifting is common to the other formats.
Signed-off-by: Jordan Crouse
---
drivers/iommu/io-pgtable-arm.c | 261 +
drivers/iommu/io-pgtable.c | 1 +
include/linux/io-pgtable.h
When DOMAIN_ATTR_SPLIT_TABLES is specified for pass ARM_64_LPAE_SPLIT_S1
to io_pgtable_ops to allocate and initialize TTBR0 and TTBR1 pagetables.
v3: Moved all the pagetable specific work into io-pgtable-arm
in a previous patch.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 16
When DOMAIN_ATTR_SPLIT_TABLES is specified for pass ARM_64_LPAE_SPLIT_S1
to io_pgtable_ops to allocate and initialize TTBR0 and TTBR1 pagetables.
v3: Moved all the pagetable specific work into io-pgtable-arm in a previous
patch.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 16
-context pagetables [2].
Thanks,
Jordan
[1] https://patchwork.freedesktop.org/series/57441/
[2] https://patchwork.freedesktop.org/patch/307616/?series=57441=3
Jordan Crouse (3):
iommu: Add DOMAIN_ATTR_SPLIT_TABLES
iommu/io-pgtable-arm: Add support for AARCH64 split pagetables
iommu/arm-smmu: Add
pagetable is selected based on the incoming iova but
most of the heavy lifting is common to the other formats.
Signed-off-by: Jordan Crouse
---
drivers/iommu/io-pgtable-arm.c | 261 +
drivers/iommu/io-pgtable.c | 1 +
include/linux/io-pgtable.h
Add a new domain attribute to enable split pagetable support for devices
devices that support it.
Signed-off-by: Jordan Crouse
---
include/linux/iommu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index fdc355c..b06db6c 100644
--- a/include
Add a new domain attribute to enable split pagetable support for devices
devices that support it.
Signed-off-by: Jordan Crouse
---
include/linux/iommu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index fdc355c..b06db6c 100644
--- a/include
.
This will be used later by the drm/msm driver to enable split pagetables
as part of the effort to implement per-context pagetables [2].
Thanks,
Jordan
[1] https://patchwork.freedesktop.org/series/57441/
[2] https://patchwork.freedesktop.org/patch/307616/?series=57441=3
Jordan Crouse (3):
iommu
On Thu, Aug 15, 2019 at 01:09:07PM +0100, Robin Murphy wrote:
> On 15/08/2019 11:56, Will Deacon wrote:
> >On Fri, Aug 09, 2019 at 06:07:52PM +0100, Robin Murphy wrote:
> >>Allocating and initialising a context for a domain is another point
> >>where certain implementations are known to want
On Wed, Aug 07, 2019 at 04:21:39PM -0600, Jordan Crouse wrote:
> Add a new sub-format ARM_ADRENO_GPU_LPAE to set up TTBR0 and TTBR1 for
> use by the Adreno GPU. This will allow The GPU driver to map global
> buffers in the TTBR1 and leave the TTBR0 configured but unset and
> free t
On Wed, Aug 07, 2019 at 04:21:38PM -0600, Jordan Crouse wrote:
> (Sigh, resend. I freaked out my SMTP server)
>
> This is part of an ongoing evolution for enabling split pagetable support for
> arm-smmu. Previous versions can be found [1].
>
> In the discussion for v2
On Mon, Aug 19, 2019 at 07:19:31PM +0100, Robin Murphy wrote:
> Now that callers are free to use a given table for TTBR1 if they wish
> (all they need do is shift the provided attributes when constructing
> their final TCR value), the only remaining impediment is the address
> validation on
On Fri, Aug 16, 2019 at 08:43:53PM +0100, Robin Murphy wrote:
> On 16/08/2019 19:12, Rob Clark wrote:
> >On Fri, Aug 16, 2019 at 9:58 AM Robin Murphy wrote:
> >>
> >>Hi Jordan,
> >>
> >>On 15/08/2019 16:33, Jordan Crouse wrote:
> >>>On W
Add a SMMU model for the Adreno GPU and use it to enable split
pagetable support if the conditions are right.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu-impl.c | 15 +++
drivers/iommu/arm-smmu.c | 2 ++
drivers/iommu/arm-smmu.h | 1 +
3 files changed, 18
for split pagetables
on arm-smmu-v2 to date and it is the easiest configuration to support
without a bunch of extra logic.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 41 +
drivers/iommu/arm-smmu.h | 1 +
2 files changed, 38 insertions
Add a new attribute to query the state of split pagetables for the domain.
Signed-off-by: Jordan Crouse
---
include/linux/iommu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index fdc355c..b06db6c 100644
--- a/include/linux/iommu.h
+++ b
Add a compatible string to identify SMMUs that are attached
to Adreno GPU devices that wish to support split pagetables.
Signed-off-by: Jordan Crouse
---
Documentation/devicetree/bindings/iommu/arm,smmu.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree
/iommu/2019-August/038244.html
[5] https://patchwork.freedesktop.org/patch/307601/
Jordan Crouse (7):
iommu/arm-smmu: Support split pagetables
dt-bindings: arm-smmu: Add Adreno GPU variant
iommu/arm-smmu: Add a SMMU variant for the Adreno GPU
iommu: Add DOMAIN_ATTR_SPLIT_TABLES
iommu/arm
Support the DOMAIN_ATTR_SPLIT_TABLES attribute to let the leaf driver
know if split pagetables are enabled for the domain.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index
On Tue, Aug 20, 2019 at 04:25:56PM +0100, Robin Murphy wrote:
> On 20/08/2019 11:31, Will Deacon wrote:
> >On Mon, Aug 19, 2019 at 07:19:30PM +0100, Robin Murphy wrote:
> >>Although it's conceptually nice for the io_pgtable_cfg to provide a
> >>standard VMSA TCR value, the reality is that no
Add a new sub-format ARM_ADRENO_GPU_LPAE to set up TTBR0 and TTBR1 for
use by the Adreno GPU. This will allow The GPU driver to map global
buffers in the TTBR1 and leave the TTBR0 configured but unset and
free to be changed dynamically by the GPU.
Signed-off-by: Jordan Crouse
---
drivers/iommu
a look and give some advice on the
direction.
[1] https://patchwork.freedesktop.org/series/63403/
Jordan
Jordan Crouse (2):
iommu/io-pgtable-arm: Add support for ARM_ADRENO_GPU_LPAE io-pgtable
format
iommu/arm-smmu: Add support for Adreno GPU pagetable formats
drivers/iommu/arm-smmu.c
Add support for an Adreno GPU variant of the arm-smmu device to enable
a special pagetable format that enables TTBR1 and leaves TTBR0 free
to be switched by the GPU hardware.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion
Add a new sub-format ARM_ADRENO_GPU_LPAE to set up TTBR0 and TTBR1 for
use by the Adreno GPU. This will allow The GPU driver to map global
buffers in the TTBR1 and leave the TTBR0 configured but unset and
free to be changed dynamically by the GPU.
Signed-off-by: Jordan Crouse
---
drivers/iommu
.
[1] https://patchwork.freedesktop.org/series/63403/
Jordan
Jordan Crouse (2):
iommu/io-pgtable-arm: Add support for ARM_ADRENO_GPU_LPAE io-pgtable
format
iommu/arm-smmu: Add support for Adreno GPU pagetable formats
drivers/iommu/arm-smmu.c | 8 +-
drivers/iommu/io-pgtable-arm.c
On Mon, Nov 04, 2019 at 07:14:45PM +, Will Deacon wrote:
> On Fri, Oct 25, 2019 at 07:08:38PM +0100, Robin Murphy wrote:
> > Although it's conceptually nice for the io_pgtable_cfg to provide a
> > standard VMSA TCR value, the reality is that no VMSA-compliant IOMMU
> > looks exactly like an
On Fri, Oct 25, 2019 at 07:08:39PM +0100, Robin Murphy wrote:
> Now that we can correctly extract top-level indices without relying on
> the remaining upper bits being zero, the only remaining impediments to
> using a given table for TTBR1 are the address validation on map/unmap
> and the awkward
On Thu, Oct 31, 2019 at 12:03:28PM +, Will Deacon wrote:
> On Wed, Oct 30, 2019 at 05:09:41PM -0600, Jordan Crouse wrote:
> > On Wed, Oct 30, 2019 at 02:51:11PM +, Will Deacon wrote:
> > > @@ -2235,12 +2237,16 @@ static const struct dev_pm_ops arm_smmu_pm_ops = {
>
On Wed, Oct 30, 2019 at 02:51:11PM +, Will Deacon wrote:
> This reverts commit addb672f200f4e99368270da205320b83efe01a0.
>
> Let's get the SMMU driver building as a module, which means putting
> back some dead code that we used to carry.
>
> Signed-off-by: Will Deacon
> ---
>
the awkward TCR translation granule format. Add a quirk so that we
> can do the right thing at those points.
Tested-by: Jordan Crouse
> Signed-off-by: Robin Murphy
> ---
> drivers/iommu/io-pgtable-arm.c | 25 +++--
> include/linux/io-pgtable.h | 4
gt; representing the allocated table. This paves the way for future users to
> support split address spaces by simply allocating a table and dealing
> with the detailed TTBRn logistics themselves.
Tested-by: Jordan Crouse
> Signed-off-by: Robin Murphy
> ---
> drivers/iommu/arm-
walk attributes.
Tested-by: Jordan Crouse
> Signed-off-by: Robin Murphy
> ---
> drivers/iommu/arm-smmu-v3.c| 41 +++--
> drivers/iommu/arm-smmu.c | 7 ++-
> drivers/iommu/arm-smmu.h | 27
> drivers/iommu/io-pgtable-arm-v7s.c
Add "qcom,adreno-smmu-v2" compatible string for the Adreno GPU SMMU node
to enable split pagetable support.
Signed-off-by: Jordan Crouse
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dt
to start swapping TTBR0 for context-specific pagetables.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 46 ++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno
successfully programmed. The
domain geometry will be updated so that the caller can determine the
start of the region to generate correct virtual addresses.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu-impl.c | 3 ++
drivers/iommu/arm-smmu-qcom.c | 96
functions to create the address space so a2xx can do its own thing in its
own space. For all the other targets use a generic helper to initialize
IOMMU but leave the door open for newer targets to use customization
if they need it.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c
Pass the propposed io_pgtable_cfg to the implementation specific
init_context() function to give the implementation an opportunity to to
modify it before it gets passed to io-pgtable.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu-impl.c | 3 ++-
drivers/iommu/arm-smmu.c | 11
Add a compatible string to identify SMMUs that are attached
to Adreno GPU devices that wish to support split pagetables.
Signed-off-by: Jordan Crouse
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree
/iommu/2019-October/039720.html
Jordan Crouse (8):
dt-bindings: arm-smmu: Add Adreno GPU variant
iommu: Add DOMAIN_ATTR_SPLIT_TABLES
iommu/arm-smmu: Pass io_pgtable_cfg to impl specific init_context
iommu/arm-smmu: Add split pagetables for Adreno IOMMU implementations
drm/msm: Attach
aggressive cleanups that follow.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 4
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 7 ---
drivers/gpu/drm/msm/msm_gem_vma.c| 23
Add a new attribute to enable and query the state of split pagetables
for the domain.
Signed-off-by: Jordan Crouse
---
include/linux/iommu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index f2223cb..18c861e 100644
--- a/include/linux
On Wed, Dec 04, 2019 at 04:44:59PM +, Robin Murphy wrote:
> On 22/11/2019 11:31 pm, Jordan Crouse wrote:
> >Add implementation specific support to enable split pagetables for
> >SMMU implementations attached to Adreno GPUs on Qualcomm targets.
> >
> >To enable
to start swapping TTBR0 for context-specific pagetables.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 52 ++-
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno
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