Hi Jacob,
On 12/3/19 7:27 AM, Jacob Pan wrote:
On Thu, 28 Nov 2019 10:25:47 +0800
Lu Baolu wrote:
This adds functions to manipulate first level page tables
which could be used by a scalale mode capable IOMMU unit.
FL and SL page tables are very similar, and I presume we are not using
all
This checks whether a domain should use the first level page
table for map/unmap and marks it in the domain structure.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 39 +
1 file changed, 39 insertions(+)
diff --git a/drivers/iommu/intel-iommu.c b
After we make all map/unmap paths support first level page table.
Let's turn it on if hardware supports scalable mode.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/
iova translation.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 48 +++--
include/linux/intel-iommu.h | 10
2 files changed, 52 insertions(+), 6 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index
PASID_FLAG_FL5LP
bit in the flags which indicates whether the 5-level paging
mode should be used.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-pasid.c | 7 ++-
drivers/iommu/intel-pasid.h | 6 ++
drivers/iommu/intel-svm.c | 8 ++--
3 files changed, 14 insertions(+), 7 deletions
he page table address binding to host's
first level.
Based-on-idea-by: Ashok Raj
Based-on-idea-by: Kevin Tian
Based-on-idea-by: Liu Yi L
Based-on-idea-by: Jacob Pan
Based-on-idea-by: Sanjay Kumar
Based-on-idea-by: Lu Baolu
Change log:
v2->v3:
- The previous version was posted here
When software has changed first-level tables, it should invalidate
the affected IOTLB and the paging-structure-caches using the PASID-
based-IOTLB Invalidate Descriptor defined in spec 6.5.2.4.
Signed-off-by: Lu Baolu
---
drivers/iommu/dmar.c| 41
nested mode, otherwise failure.
Signed-off-by: Yi Sun
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 56 +
1 file changed, 56 insertions(+)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index c93fe716e6b0..2b5a47584baf
Hi,
On 12/12/19 12:35 AM, Jerry Snitselaar wrote:
On Wed Dec 11 19, Lu Baolu wrote:
If the default DMA domain of a group doesn't fit a device, it
will still sit in the group but use a private identity domain.
When map/unmap/iova_to_phys come through iommu API, the driver
should still
rced
by drivers such as vfio.
Fixes: d850c2ee5fe2 ("iommu/vt-d: Expose ISA direct mapping region via
iommu_get_resv_regions")
Cc: sta...@vger.kernel.org # v5.3+
Link: https://lore.kernel.org/linux-iommu/20191211082304.2d4fa...@x1.home
Reported-by: cprt
Tested-by: cprt
Signed-off-by: Alex
Hi,
On 12/12/19 9:49 AM, Jerry Snitselaar wrote:
On Wed Dec 11 19, Lu Baolu wrote:
If the default DMA domain of a group doesn't fit a device, it
will still sit in the group but use a private identity domain.
When map/unmap/iova_to_phys come through iommu API, the driver
should still serve
Hi,
On 12/12/19 3:46 AM, Barret Rhoden via iommu wrote:
I can imagine a bunch of ways around this.
One option is to hook in a check for buggy RMRRs in intel-iommu.c. If
the base and end are 0, just ignore the entry. That works for my
specific buggy DMAR entry. There might be other buggy entr
Hi,
On 12/13/19 8:30 AM, Jerry Snitselaar wrote:
On Thu Dec 12 19, Lu Baolu wrote:
Hi,
On 12/12/19 9:49 AM, Jerry Snitselaar wrote:
On Wed Dec 11 19, Lu Baolu wrote:
If the default DMA domain of a group doesn't fit a device, it
will still sit in the group but use a private identity d
Hi,
On 12/13/19 11:16 AM, Jerry Snitselaar wrote:
On Thu Dec 12 19, Jerry Snitselaar wrote:
On Fri Dec 13 19, Lu Baolu wrote:
Hi,
On 12/13/19 8:30 AM, Jerry Snitselaar wrote:
On Thu Dec 12 19, Lu Baolu wrote:
Hi,
On 12/12/19 9:49 AM, Jerry Snitselaar wrote:
On Wed Dec 11 19, Lu Baolu
Hi Jerry,
On 12/13/19 1:36 PM, Jerry Snitselaar wrote:
Currently the reserved region for ISA is allocated with no
permissions. If a dma domain is being used, mapping this region will
fail. Set the permissions to DMA_PTE_READ|DMA_PTE_WRITE.
Cc: Joerg Roedel
Cc: Lu Baolu
Cc: iommu@lists.linux
On 12/13/19 10:31 PM, Barret Rhoden wrote:
On 12/11/19 9:43 PM, Lu Baolu wrote:
The VT-d spec defines the BIOS considerations about RMRR in section 8.4:
"
BIOS must report the RMRR reported memory addresses as reserved (or as
EFI runtime) in the system memory map returned through methods
Hi Liu Yi,
Thanks for reviewing my patch.
On 12/13/19 5:23 PM, Liu, Yi L wrote:
From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org] On Behalf
Of Lu Baolu
Sent: Wednesday, December 11, 2019 10:12 AM
Subject: [PATCH v3 4/6] iommu/vt-d: Setup pasid entries for iova over first
Hi Liu Yi,
On 12/13/19 7:42 PM, Liu, Yi L wrote:
From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org] On Behalf
Of Lu Baolu
Sent: Wednesday, December 11, 2019 10:12 AM
To: Joerg Roedel ; David Woodhouse ;
Subject: [PATCH v3 5/6] iommu/vt-d: Flush PASID-based iotlb for iova over
Hi Jerry,
On 12/14/19 9:42 AM, Lu Baolu wrote:
Hi Jerry,
On 12/13/19 1:36 PM, Jerry Snitselaar wrote:
Currently the reserved region for ISA is allocated with no
permissions. If a dma domain is being used, mapping this region will
fail. Set the permissions to DMA_PTE_READ|DMA_PTE_WRITE.
Cc
Hi,
On 12/13/19 1:36 PM, Jerry Snitselaar wrote:
Currently the reserved region for ISA is allocated with no
permissions. If a dma domain is being used, mapping this region will
fail. Set the permissions to DMA_PTE_READ|DMA_PTE_WRITE.
Cc: Joerg Roedel
Cc: Lu Baolu
Cc: iommu@lists.linux
Hi Yi,
On 12/15/19 5:22 PM, Liu, Yi L wrote:
Ok, let me explain more... default pasid is meaningful only when
the domain has been attached to a device as an aux-domain. right?
No exactly. Each domain has a specific default pasid, no matter normal
domain (RID based) or aux-domain (PASID based).
Hi again,
On 12/17/19 9:19 AM, Lu Baolu wrote:
Hi Yi,
On 12/15/19 5:22 PM, Liu, Yi L wrote:
Ok, let me explain more... default pasid is meaningful only when
the domain has been attached to a device as an aux-domain. right?
No exactly. Each domain has a specific default pasid, no matter
Hi,
On 12/17/19 9:37 AM, Lu Baolu wrote:
You are right. I will change it accordingly. The logic should look
like:
if (domain attached to physical device)
flush_piotlb_with_RID2PASID()
else if (domain_attached_to_mdev_device)
flush_piotlb_with_default_pasid()
Both! so no "
Hi Yi,
On 12/15/19 5:37 PM, Liu, Yi L wrote:
XD (bit 63) is only for the first level, and SNP (bit 11) is only for second
level, right? I
think we need to always set XD bit for IOVA over FL case. thoughts?
Oops, I made a mistake here. Please forget SNP bit, there is no way to control
SNP
with
Hi,
On 2019/12/17 10:36, Liu, Yi L wrote:
From: Liu, Yi L
Sent: Tuesday, December 17, 2019 10:26 AM
To: Lu Baolu ; Joerg Roedel ; David
Woodhouse ; Alex Williamson
Subject: RE: [PATCH v3 5/6] iommu/vt-d: Flush PASID-based iotlb for iova over
first
level
From: Lu Baolu [mailto:baolu
Hi Jacob,
On 12/17/19 3:24 AM, Jacob Pan wrote:
Nested translation mode is supported in VT-d 3.0 Spec.CH 3.8.
With PASID granular translation type set to 0x11b, translation
result from the first level(FL) also subject to a second level(SL)
page table translation. This mode is used for SVA virtua
Hi again,
On 12/17/19 3:24 AM, Jacob Pan wrote:
+/**
+ * intel_pasid_setup_nested() - Set up PASID entry for nested translation
+ * which is used for vSVA. The first level page tables are used for
+ * GVA-GPA or GIOVA-GPA translation in the guest, second level page tables
+ * are used for GPA-H
Hi,
On 12/17/19 3:24 AM, Jacob Pan wrote:
When supporting guest SVA with emulated IOMMU, the guest PASID
table is shadowed in VMM. Updates to guest vIOMMU PASID table
will result in PASID cache flush which will be passed down to
the host as bind guest PASID calls.
For the SL page tables, it wil
Hi,
On 12/17/19 3:24 AM, Jacob Pan wrote:
Virtual command registers are used in the guest only, to prevent
vmexit cost, we cache the capability and store it during initialization.
Signed-off-by: Jacob Pan
---
drivers/iommu/dmar.c| 1 +
include/linux/intel-iommu.h | 4
2 files
always
come from the host. This ensures that PASID namespace is system-
wide.
Signed-off-by: Lu Baolu
Signed-off-by: Liu, Yi L
Signed-off-by: Jacob Pan
---
drivers/iommu/intel-iommu.c | 75 +
include/linux/intel-iommu.h | 2 ++
2 files changed, 77
Please tweak the title to
"iommu/vt-d: Use generic_iommu_put_resv_regions()"
then,
Acked-by: Lu Baolu
Best regards,
baolu
On 12/18/19 9:42 PM, Thierry Reding wrote:
From: Thierry Reding
Use the new standard function instead of open-coding it.
Cc: David Woodhouse
Signed-off-b
Hi,
On 12/17/19 3:24 AM, Jacob Pan wrote:
When Shared Virtual Memory is exposed to a guest via vIOMMU, scalable
IOTLB invalidation may be passed down from outside IOMMU subsystems.
This patch adds invalidation functions that can be used for additional
translation cache types.
Signed-off-by: Jac
nested mode, otherwise failure.
Signed-off-by: Yi Sun
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 56 +
1 file changed, 56 insertions(+)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index c93fe716e6b0..2b5a47584baf
When software has changed first-level tables, it should invalidate
the affected IOTLB and the paging-structure-caches using the PASID-
based-IOTLB Invalidate Descriptor defined in spec 6.5.2.4.
Signed-off-by: Lu Baolu
---
drivers/iommu/dmar.c| 41 +++
drivers
he page table address binding to host's
first level.
Based-on-idea-by: Ashok Raj
Based-on-idea-by: Kevin Tian
Based-on-idea-by: Liu Yi L
Based-on-idea-by: Jacob Pan
Based-on-idea-by: Sanjay Kumar
Based-on-idea-by: Lu Baolu
Change log:
v3->v4:
- The previous version was posted here
PASID_FLAG_FL5LP
bit in the flags which indicates whether the 5-level paging
mode should be used.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-pasid.c | 7 ++-
drivers/iommu/intel-pasid.h | 6 ++
drivers/iommu/intel-svm.c | 8 ++--
3 files changed, 14 insertions(+), 7 deletions
This checks whether a domain should use the first level page
table for map/unmap and marks it in the domain structure.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 39 +
1 file changed, 39 insertions(+)
diff --git a/drivers/iommu/intel-iommu.c b
After we make all map/unmap paths support first level page table.
Let's turn it on if hardware supports scalable mode.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/
iova translation.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 48 +++--
include/linux/intel-iommu.h | 16 -
2 files changed, 56 insertions(+), 8 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index
0x00015f3dc003 0x8ced7003
0x00015f3db003 0x00015f3dc003 0x8ced8003
0x00015f3db003 0x00015f3dc003 0x8ced9003
[ ... ]
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu-debugfs.c | 75 +
drivers
Currently if flush queue initialization fails, we return error
or enforce the system-wide strict mode. These are unnecessary
because we always check the existence of a flush queue before
queuing any iova's for lazy flushing. Printing a informational
message is enough.
Signed-off-by: Lu
If Intel IOMMU strict mode is enabled by users, it's unnecessary
to create the iova flush queue.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/
Hi Yi,
On 12/20/19 7:44 PM, Liu, Yi L wrote:
From: Lu Baolu [mailto:baolu...@linux.intel.com]
Sent: Thursday, December 19, 2019 11:17 AM
To: Joerg Roedel ; David Woodhouse ;
Alex Williamson
Subject: [PATCH v4 4/7] iommu/vt-d: Setup pasid entries for iova over first
level
Intel VT-d in
Hi Yi,
Thanks for the comments.
On 12/20/19 7:50 PM, Liu, Yi L wrote:
Hi Baolu,
In a brief, this version is pretty good to me. However, I still want
to have the following checks to see if anything missed. Wish it
helps.
1) would using IOVA over FLPT default on?
My opinion is that before we ha
Hi again,
On 2019/12/20 19:50, Liu, Yi L wrote:
3) Per VT-d spec, FLPT has canonical requirement to the input
addresses. So I'd suggest to add some enhance regards to it.
Please refer to chapter 3.6:-).
3.6 First-Level Translation
First-level translation restricts the input-address to a canonic
Hi Yi,
On 12/21/19 11:14 AM, Lu Baolu wrote:
Hi again,
On 2019/12/20 19:50, Liu, Yi L wrote:
3) Per VT-d spec, FLPT has canonical requirement to the input
addresses. So I'd suggest to add some enhance regards to it.
Please refer to chapter 3.6:-).
3.6 First-Level Translation
First-
Hi,
On 12/21/19 11:03 PM, Tom Murphy wrote:
@@ -5618,9 +5583,13 @@ static int intel_iommu_add_device(struct device *dev)
struct iommu_domain *domain;
struct intel_iommu *iommu;
struct iommu_group *group;
+ u64 dma_mask = *dev->dma_mask;
u8 bus, devfn;
Hi,
On 2019/12/23 15:59, Jim,Yan wrote:
-邮件原件-
发件人: Jerry Snitselaar [mailto:jsnit...@redhat.com]
发送时间: 2019年12月20日 17:23
收件人: Jim,Yan
抄送: j...@8bytes.org; iommu@lists.linux-foundation.org;
linux-ker...@vger.kernel.org
主题: Re: [PATCH] iommu/vt-d: Don't reject nvme host due to scope mism
: Roland Dreier
Cc: Jim Yan
Signed-off-by: Lu Baolu
---
drivers/iommu/dmar.c | 37 +++--
1 file changed, 23 insertions(+), 14 deletions(-)
diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c
index fb30d5053664..fc24abc70a05 100644
--- a/drivers/iommu/dmar.c
+++ b
Hi Jim,
On 2019/12/24 11:24, Jim,Yan wrote:
-邮件原件-
发件人: Lu Baolu [mailto:baolu...@linux.intel.com]
发送时间: 2019年12月23日 21:05
收件人: Jim,Yan ; Jerry Snitselaar
抄送: iommu@lists.linux-foundation.org; linux-ker...@vger.kernel.org
主题: Re: 答复: [PATCH] iommu/vt-d: Don't reject nvme host d
This checks whether a domain should use the first level page
table for map/unmap and marks it in the domain structure.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 39 +
1 file changed, 39 insertions(+)
diff --git a/drivers/iommu/intel-iommu.c b
nested mode, otherwise failure.
Signed-off-by: Yi Sun
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 56 +
1 file changed, 56 insertions(+)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index 71ad5e5feae2..35f65628202c
iova translation.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 57 +
include/linux/intel-iommu.h | 16 +++
2 files changed, 62 insertions(+), 11 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index
: Lu Baolu
---
drivers/iommu/intel-iommu.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index 1ebf5ed460cf..34e619318f64 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
When software has changed first-level tables, it should invalidate
the affected IOTLB and the paging-structure-caches using the PASID-
based-IOTLB Invalidate Descriptor defined in spec 6.5.2.4.
Signed-off-by: Lu Baolu
---
drivers/iommu/dmar.c| 41 +++
drivers
0x00015f3dc003 0x8ced7003
0x00015f3db003 0x00015f3dc003 0x8ced8003
0x00015f3db003 0x00015f3dc003 0x8ced9003
[ ... ]
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu-debugfs.c | 75 +
drivers
bit [N-1]
always cleared.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index 54db6bc0b281..1ebf5ed460cf 100644
--- a/drivers/iommu/intel
PASID_FLAG_FL5LP
bit in the flags which indicates whether the 5-level paging
mode should be used.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-pasid.c | 7 ++-
drivers/iommu/intel-pasid.h | 6 ++
drivers/iommu/intel-svm.c | 8 ++--
3 files changed, 14 insertions(+), 7 deletions
he page table address binding to host's
first level.
Based-on-idea-by: Ashok Raj
Based-on-idea-by: Kevin Tian
Based-on-idea-by: Liu Yi L
Based-on-idea-by: Jacob Pan
Based-on-idea-by: Sanjay Kumar
Based-on-idea-by: Lu Baolu
Change log:
v4->v5:
- The previous version was posted
After we make all map/unmap paths support first level page table.
Let's turn it on if hardware supports scalable mode.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/
Hi,
On 2019/12/24 16:18, Jim,Yan wrote:
For both cases, a quirk flag seems to be more reasonable, so that
unrelated devices will not be impacted.
Best regards,
baolu
Hi Baolu,
Thanks for your advice. And I modify the patch as follow.
I just posted a patch for both NTG and NVME cases.
Hi,
On 2019/12/25 9:52, Jim,Yan wrote:
Hi,
-邮件原件-
发件人: Lu Baolu [mailto:baolu...@linux.intel.com]
发送时间: 2019年12月24日 19:27
收件人: Jim,Yan ; Jerry Snitselaar
抄送: iommu@lists.linux-foundation.org; linux-ker...@vger.kernel.org
主题: Re: 答复: 答复: 答复: [PATCH] iommu/vt-d: Don't reject nvme
Hi,
On 12/25/19 10:05 AM, Jim,Yan wrote:
Hi,
-邮件原件-
发件人: Lu Baolu [mailto:baolu...@linux.intel.com]
发送时间: 2019年12月25日 10:01
收件人: Jim,Yan ; Jerry Snitselaar
抄送: iommu@lists.linux-foundation.org; linux-ker...@vger.kernel.org
主题: Re: 答复: 答复: 答复: 答复: [PATCH] iommu/vt-d: Don't reject
On 11/12/19 2:39 PM, Lu Baolu wrote:
This adds Kconfig option INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON
to make it easier for distributions to enable or disable the
Intel IOMMU scalable mode by default during kernel build.
Signed-off-by: Lu Baolu
Queued for v5.6.
Thanks,
-baolu
On 12/3/19 3:58 AM, Jacob Pan wrote:
Mostly extracted from nested SVA/SVM series based on review comments of v7.
https://lkml.org/lkml/2019/10/24/852
This series also adds a few important fixes for native use of SVA. Nested
SVA new code will be submitted separately as a smaller set. Based on the
On 12/19/19 1:18 PM, Lu Baolu wrote:
Currently if flush queue initialization fails, we return error
or enforce the system-wide strict mode. These are unnecessary
because we always check the existence of a flush queue before
queuing any iova's for lazy flushing. Printing a informational
me
On 12/19/19 1:18 PM, Lu Baolu wrote:
If Intel IOMMU strict mode is enabled by users, it's unnecessary
to create the iova flush queue.
Signed-off-by: Lu Baolu
Queued for v5.6.
Thanks,
-baolu
___
iommu mailing list
iommu@lists.linux-foundatio
On 12/11/19 9:42 AM, Lu Baolu wrote:
Current map_sg stores trace message in a coarse manner. This
extends it so that more detailed messages could be traced.
The map_sg trace message looks like:
map_sg: dev=:00:17.0 [1/9] dev_addr=0xf8f9 phys_addr=0x158051000
size=4096
map_sg: dev=
ing a platform device to user level as
far as I can see, so though this fix is not the best, it won't break
anything. I will ack this fix so that the kernel crash could be fixed
before we figure out a better solution.
Cc: sta...@vger.kernel.org # v5.3+
Acked-by: Lu Baolu
Best regards,
-bao
Hi,
On 1/1/20 4:24 AM, Jon Derrick wrote:
This adds the missing teardown step that removes the device link from
the group when the device addition fails.
This change looks good to me.
Reviewed-by: Lu Baolu
Best regards,
baolu
Signed-off-by: Jon Derrick
---
drivers/iommu/iommu.c | 1
On 1/1/20 4:24 AM, Jon Derrick wrote:
If the device fails to be added to the group, make sure to unlink the
reference before returning.
Signed-off-by: Jon Derrick
This fix looks reasonable to me.
Acked-by: Lu Baolu
Best regards,
baolu
---
drivers/iommu/intel-iommu.c | 13
kernel command
parameters.
Signed-off-by: Lu Baolu
---
include/linux/device.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/linux/device.h b/include/linux/device.h
index 96ff76731e93..763d2d078d34 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -1247,6 +1247,8
Determine the default domain type for each group and use it to
allocate the iommu domain.
Signed-off-by: Lu Baolu
---
drivers/iommu/iommu.c | 35 ---
1 file changed, 32 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
The new parameter takes a list of devices separated by a semicolon.
Each device specified will have its iommu_passthrough bit in struct
device set. This is very similar to the existing 'disable_acs_redir'
parameter.
Signed-off-by: Lu Baolu
---
.../admin-guide/kernel-parameters.txt
This splits iommu group allocation from adding devices. This makes
it possible to determine the default domain type for each group as
all devices belonging to the group have been determined.
Signed-off-by: Lu Baolu
---
drivers/iommu/iommu.c | 92 +++
1
precedure to determine a per-group
default domain type before allocating IOMMU domains and attaching them
to devices.
Please help to review it. Your comments and suggestions are appricated.
Best regards,
baolu
Lu Baolu (4):
driver core: Add iommu_passthrough to struct device
PCI: Add &quo
On 12/24/19 2:22 PM, Lu Baolu wrote:
We expect devices with endpoint scope to have normal PCI headers,
and devices with bridge scope to have bridge PCI headers. However
Some PCI devices may be listed in the DMAR table with bridge scope,
even though they have a normal PCI header. Add a quirk
On 12/24/19 3:44 PM, Lu Baolu wrote:
Intel VT-d in scalable mode supports two types of page tables
for DMA translation: the first level page table and the second
level page table. The first level page table uses the same
format as the CPU page table, while the second level page table
keeps
iova translation.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 57 +
include/linux/intel-iommu.h | 16 +++
2 files changed, 62 insertions(+), 11 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index
0x00015f3dc003 0x8ced7003
0x00015f3db003 0x00015f3dc003 0x8ced8003
0x00015f3db003 0x00015f3dc003 0x8ced9003
[ ... ]
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu-debugfs.c | 75 +
drivers
From: Jacob Pan
Make use of generic IOASID code to manage PASID allocation,
free, and lookup. Replace Intel specific code.
Signed-off-by: Jacob Pan
Reviewed-by: Eric Auger
Signed-off-by: Lu Baolu
---
drivers/iommu/Kconfig | 1 +
drivers/iommu/intel-iommu.c | 13 +++--
drivers
=0x148351000
size=4096
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c| 7 +++--
include/trace/events/intel_iommu.h | 48 ++
2 files changed, 47 insertions(+), 8 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index
nested mode, otherwise failure.
Signed-off-by: Yi Sun
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 56 +
1 file changed, 56 insertions(+)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index 71ad5e5feae2..35f65628202c
eviewed-by: Eric Auger
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-svm.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c
index f0410e29fbc1..7c6a6e8b1c96 100644
--- a/drivers/iommu/intel-svm.c
+++ b/drivers/i
From: Jacob Pan
PASID allocator uses IDR which is exclusive for the end of the
allocation range. There is no need to decrement pasid_max.
Fixes: af39507305fb ("iommu/vt-d: Apply global PASID in SVA")
Reported-by: Eric Auger
Signed-off-by: Jacob Pan
Reviewed-by: Eric Auger
Signed-
This checks whether a domain should use the first level page
table for map/unmap and marks it in the domain structure.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 39 +
1 file changed, 39 insertions(+)
diff --git a/drivers/iommu/intel-iommu.c b
PASID_FLAG_FL5LP
bit in the flags which indicates whether the 5-level paging
mode should be used.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-pasid.c | 7 ++-
drivers/iommu/intel-pasid.h | 6 ++
drivers/iommu/intel-svm.c | 8 ++--
3 files changed, 14 insertions(+), 7 deletions
From: Jacob Pan
Add a check during SVM bind to ensure CPU and IOMMU hardware capabilities
are met.
Signed-off-by: Jacob Pan
Reviewed-by: Eric Auger
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-svm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/intel-svm.c b
This adds Kconfig option INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON
to make it easier for distributions to enable or disable the
Intel IOMMU scalable mode by default during kernel build.
Signed-off-by: Lu Baolu
---
drivers/iommu/Kconfig | 12
drivers/iommu/intel-iommu.c | 7
From: Jacob Pan
Use combined macros for_each_svm_dev() to simplify SVM device iteration
and error checking.
Suggested-by: Andy Shevchenko
Signed-off-by: Jacob Pan
Reviewed-by: Eric Auger
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-svm.c | 79 +++
1
After we make all map/unmap paths support first level page table.
Let's turn it on if hardware supports scalable mode.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/
: Lu Baolu
---
drivers/iommu/intel-iommu.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index 1ebf5ed460cf..34e619318f64 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
From: Jacob Pan
After each setup for PASID entry, related translation caches must be
flushed. We can combine duplicated code into one function which is less
error prone.
Signed-off-by: Jacob Pan
Reviewed-by: Eric Auger
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-pasid.c | 48
, these error message
shall never appear in kernel log.
Signed-off-by: Jacob Pan
Reviewed-by: Eric Auger
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 10 ++
drivers/iommu/intel-svm.c | 40 +
include/linux/intel-iommu.h | 5 -
3 files
If Intel IOMMU strict mode is enabled by users, it's unnecessary
to create the iova flush queue.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/
bit [N-1]
always cleared.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index 54db6bc0b281..1ebf5ed460cf 100644
--- a/drivers/iommu/intel
Currently if flush queue initialization fails, we return error
or enforce the system-wide strict mode. These are unnecessary
because we always check the existence of a flush queue before
queuing any iova's for lazy flushing. Printing a informational
message is enough.
Signed-off-by: Lu
response
iommu/vt-d: Misc macro clean up for SVM
Lu Baolu (14):
iommu/vt-d: Add Kconfig option to enable/disable scalable mode
iommu/vt-d: trace: Extend map_sg trace event
iommu/vt-d: Avoid iova flush queue in strict mode
iommu/vt-d: Loose requirement for flush queue initializaton
iommu
table interface")
Signed-off-by: Jacob Pan
Reviewed-by: Eric Auger
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-pasid.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c
index 040a445be300..e7cb0b8a7
When software has changed first-level tables, it should invalidate
the affected IOTLB and the paging-structure-caches using the PASID-
based-IOTLB Invalidate Descriptor defined in spec 6.5.2.4.
Signed-off-by: Lu Baolu
---
drivers/iommu/dmar.c| 41 +++
drivers
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