On Wed, Sep 25, 2013 at 10:49 AM, Joerg Roedel j...@8bytes.org wrote:
The function msm_iommu_get_ctx() is needed buy the MSM-GPU
driver with and wiithout IOMMU compiled in. Make the
function available when no IOMMU driver is there.
For this one,
Reviewed-by: Rob Clark robdcl...@gmail.com
On Wed, Jan 8, 2014 at 8:35 AM, Joerg Roedel j...@8bytes.org wrote:
On Wed, Jan 08, 2014 at 08:23:49AM -0500, Rob Clark wrote:
On Tue, Jan 7, 2014 at 5:53 PM, Joerg Roedel j...@8bytes.org wrote:
On Tue, Jan 07, 2014 at 11:47:26PM +0100, Joerg Roedel wrote:
The DRM driver for MSM depends
On Tue, Jul 8, 2014 at 5:53 PM, Olav Haugan ohau...@codeaurora.org wrote:
Hi Hiroshi,
On 7/3/2014 9:29 PM, Hiroshi Doyu wrote:
Hi Olav,
Olav Haugan ohau...@codeaurora.org writes:
Mapping and unmapping are more often than not in the critical path.
map_range and unmap_range allows SMMU
On Wed, Jul 9, 2014 at 8:03 PM, Olav Haugan ohau...@codeaurora.org wrote:
On 7/8/2014 4:49 PM, Rob Clark wrote:
On Tue, Jul 8, 2014 at 5:53 PM, Olav Haugan ohau...@codeaurora.org wrote:
Hi Hiroshi,
On 7/3/2014 9:29 PM, Hiroshi Doyu wrote:
Hi Olav,
Olav Haugan ohau...@codeaurora.org writes
On Thu, Jul 10, 2014 at 3:10 AM, Thierry Reding
thierry.red...@gmail.com wrote:
On Wed, Jul 09, 2014 at 08:40:21PM -0400, Rob Clark wrote:
On Wed, Jul 9, 2014 at 8:03 PM, Olav Haugan ohau...@codeaurora.org wrote:
On 7/8/2014 4:49 PM, Rob Clark wrote:
On Tue, Jul 8, 2014 at 5:53 PM, Olav
Moskovchenko step...@codeaurora.org);
+MODULE_AUTHOR(Rob Clark robdcl...@gmail.com);
diff --git a/drivers/iommu/qcom_iommu_v0.h b/drivers/iommu/qcom_iommu_v0.h
new file mode 100644
index 000..efe8535
--- /dev/null
+++ b/drivers/iommu/qcom_iommu_v0.h
@@ -0,0 +1,95 @@
+/* Copyright (c) 2010-2011, Code
On Thu, Jul 10, 2014 at 6:43 PM, Olav Haugan ohau...@codeaurora.org wrote:
On 7/9/2014 5:40 PM, Rob Clark wrote:
On Wed, Jul 9, 2014 at 8:03 PM, Olav Haugan ohau...@codeaurora.org wrote:
On 7/8/2014 4:49 PM, Rob Clark wrote:
On Tue, Jul 8, 2014 at 5:53 PM, Olav Haugan ohau...@codeaurora.org
On Thu, Jul 10, 2014 at 5:53 PM, Stephen Boyd sb...@codeaurora.org wrote:
On 07/10, Rob Clark wrote:
So, in it's current form, this is superficially a copy of msm_iommu
plus DT conversion. But the pre-DT IOMMU driver had fairly different
structure.. ie. psuedo root device, with IOMMU devices
On Fri, Jul 4, 2014 at 11:29 AM, Thierry Reding
thierry.red...@gmail.com wrote:
From: Thierry Reding tred...@nvidia.com
This commit introduces a generic device tree binding for IOMMU devices.
Only a very minimal subset is described here, but it is enough to cover
the requirements of both the
On Sat, Jul 12, 2014 at 5:39 AM, Will Deacon will.dea...@arm.com wrote:
Hi Rob,
On Fri, Jul 11, 2014 at 09:55:14PM +0100, Rob Clark wrote:
On Fri, Jul 4, 2014 at 11:29 AM, Thierry Reding
thierry.red...@gmail.com wrote:
From: Thierry Reding tred...@nvidia.com
ok, so I was working through
On Sat, Jul 12, 2014 at 8:22 AM, Arnd Bergmann a...@arndb.de wrote:
On Saturday 12 July 2014, Rob Clark wrote:
Was there actually a good reason for having the device link to the
iommu rather than the other way around? How much would people hate it
if I just ignore the generic bindings
On Sun, Jul 13, 2014 at 5:43 AM, Will Deacon will.dea...@arm.com wrote:
On Sat, Jul 12, 2014 at 01:57:31PM +0100, Rob Clark wrote:
On Sat, Jul 12, 2014 at 8:22 AM, Arnd Bergmann a...@arndb.de wrote:
On Saturday 12 July 2014, Rob Clark wrote:
Was there actually a good reason for having
On Mon, Jul 14, 2014 at 2:24 AM, Thierry Reding
thierry.red...@gmail.com wrote:
On Sat, Jul 12, 2014 at 08:57:31AM -0400, Rob Clark wrote:
On Sat, Jul 12, 2014 at 8:22 AM, Arnd Bergmann a...@arndb.de wrote:
[...]
The way that Thierry's binding does that is the obvious solution
On Tue, Jul 15, 2014 at 9:25 PM, Olav Haugan ohau...@codeaurora.org wrote:
On 7/13/2014 4:43 AM, Rob Clark wrote:
On Sun, Jul 13, 2014 at 5:43 AM, Will Deacon will.dea...@arm.com wrote:
On Sat, Jul 12, 2014 at 01:57:31PM +0100, Rob Clark wrote:
On Sat, Jul 12, 2014 at 8:22 AM, Arnd Bergmann
On Mon, Jul 21, 2014 at 8:59 PM, Olav Haugan ohau...@codeaurora.org wrote:
On 7/17/2014 1:21 AM, Thierry Reding wrote:
On Wed, Jul 16, 2014 at 06:01:57PM -0700, Olav Haugan wrote:
Mapping and unmapping are more often than not in the critical path.
map_range and unmap_range allows SMMU driver
On Mon, Aug 11, 2014 at 9:51 PM, Hiroshi Doyu hd...@nvidia.com wrote:
Hi Olav,
Olav Haugan ohau...@codeaurora.org writes:
@@ -93,6 +94,10 @@ enum iommu_attr {
* @detach_dev: detach device from an iommu domain
* @map: map a physically contiguous memory region to an iommu domain
*
On Mon, Aug 18, 2014 at 10:07 AM, j...@8bytes.org j...@8bytes.org wrote:
On Tue, Aug 12, 2014 at 09:56:11AM -0700, Olav Haugan wrote:
On 8/12/2014 3:48 AM, Rob Clark wrote:
iirc, one plan for 'flags' was some sort of DONT_FLUSH_TLB flag for
drivers which wanted to map/unmap N buffers
On Mon, Dec 1, 2014 at 11:57 AM, Will Deacon will.dea...@arm.com wrote:
This patch extends of_dma_configure so that it sets up the IOMMU for a
device, as well as the coherent/non-coherent DMA mapping ops.
Acked-by: Arnd Bergmann a...@arndb.de
Acked-by: Marek Szyprowski
On Wed, Feb 4, 2015 at 1:54 PM, Olav Haugan ohau...@codeaurora.org wrote:
Adding Mitch H. and Rob Clark.
The current upstream msm-iommu isn't actually used by anything,
afaict.. it lacks support for DT based platforms. So this is fine by
me.
Acked-by: Rob Clark robdcl...@gmail.com
On 2/3
through generic iommu bindings.
>
> This is essentially rework of the patch posted earlier by
> Rob Clark <robdcl...@gmail.com>. This series folds the changes in to the
> existing driver with the addition of generic bindings.
>
> http://www.spinics.net/lists/linux-arm-msm/msg10
On Thu, Aug 11, 2016 at 4:11 PM, Rob Clark <robdcl...@gmail.com> wrote:
> On Mon, Jun 13, 2016 at 7:36 AM, Sricharan R <sricha...@codeaurora.org> wrote:
>> The msm_iommu.c driver currently works based on platform data.
>> A single master device can be connected to more
On Fri, Aug 12, 2016 at 3:00 AM, Sricharan wrote:
> Hi Rob,
>
>>> btw, the current state, at least on linaro integration branch, fault
>>> handling doesn't work so well (ie. device never gets resumed).. which
>>> is a bit unfortunate for a gpu (and results in a *lot* of
On Fri, Aug 12, 2016 at 9:03 AM, Sricharan wrote:
> Hi Rob,
>
> btw, the current state, at least on linaro integration branch, fault
> handling doesn't work so well (ie. device never gets resumed).. which
> is a bit unfortunate for a gpu (and results in a
On Fri, Aug 12, 2016 at 9:48 AM, Sricharan wrote:
> Hi,
>
>>> btw, the current state, at least on linaro integration branch, fault
>>> handling doesn't work so well (ie. device never gets resumed).. which
>>> is a bit unfortunate for a gpu (and results in a
from drm/msm's fault handler instead.
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
drivers/iommu/msm_iommu.c | 16 +++-
drivers/iommu/msm_iommu.h | 3 +++
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c
PU had actually hung and reset it.
>>
>>Wire up the fault reporting, so instead we get a small ratelimited print
>>of the fault address from drm/msm's fault handler instead.
>>
>>Signed-off-by: Rob Clark <robdcl...@gmail.com>
>>---
>> drivers/iommu/msm_iommu.c
A new flag when registering the fault handler indicates that the user
supports stalling, and will call iommu_domain_resume() at some point
later, potentially from a workqueue. (This would allow the user to do
mm related operations that could not be done from irq context.)
Signed-off-by: Rob
TODO maybe some dev_dbg() or some other way to tell if stalling is
actually enabled?
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
.../devicetree/bindings/iommu/arm,smmu.txt | 3 +
drivers/iommu/arm-smmu.c | 85 --
2 files chang
Rob Clark (3):
iommu: introduce stall/resume support
iommu/arm-smmu: Add support to opt-in to stalling
iommu/arm-smmu: detach DMA domain if driver is managing iommu
.../devicetree/bindings/iommu/arm,smmu.txt | 3 +
drivers/gpu/drm/etnaviv/etnaviv_mmu.c | 2
.
(And will cause further problems later)
One simple way to deal with this is simply toss the default _DMA domain
if the driver attaches it's own domain.
TODO maybe the tracking of list of attached domains should be done in
iommu core, so the detach can happen outside of group->mutex.
Signed-off-by: Rob Cl
On Wed, Feb 1, 2017 at 10:23 AM, Rob Clark <robdcl...@gmail.com> wrote:
> Before the driver is probed, arm_smmu_add_device() helpfully attaches
> an IOMMU_DOMAIN_DMA domain. Which ofc does not support stalling, and
> when the driver later attaches a domain that can_stall to an
On Wed, Feb 1, 2017 at 11:10 PM, Sricharan <sricha...@codeaurora.org> wrote:
> Hi Rob,
>
>>On Wed, Feb 1, 2017 at 10:23 AM, Rob Clark <robdcl...@gmail.com> wrote:
>>> Before the driver is probed, arm_smmu_add_device() helpfully attaches
>>> an IOMMU_DOMA
On Thu, Jan 26, 2017 at 12:18 PM, Joerg Roedel wrote:
> On Tue, Jan 24, 2017 at 08:42:23PM +0530, Sricharan wrote:
>> Thanks for this series. We had a case with the GPU.
>> The GPU's iommu was setup by kernel and the GPU
>> also does dynamic updates for on-the-fly switching
On Wed, Feb 1, 2017 at 11:10 PM, Sricharan <sricha...@codeaurora.org> wrote:
> Hi Rob,
>
>>On Wed, Feb 1, 2017 at 10:23 AM, Rob Clark <robdcl...@gmail.com> wrote:
>>> Before the driver is probed, arm_smmu_add_device() helpfully attaches
>>> an IOMMU_DOMA
On Thu, Feb 2, 2017 at 10:12 AM, Will Deacon <will.dea...@arm.com> wrote:
> On Thu, Feb 02, 2017 at 10:02:50AM -0500, Rob Clark wrote:
>> On Thu, Jan 26, 2017 at 12:18 PM, Joerg Roedel <j...@8bytes.org> wrote:
>> > On Tue, Jan 24, 2017 at 08:42:23PM +0530,
On Thu, Jan 12, 2017 at 10:17 AM, Will Deacon <will.dea...@arm.com> wrote:
> On Wed, Jan 11, 2017 at 03:59:30PM -0500, Rob Clark wrote:
>> On Wed, Jan 11, 2017 at 4:36 AM, Will Deacon <will.dea...@arm.com> wrote:
>> > On Tue, Jan 10, 2017 at 02:20:13PM -0500, Rob Cla
On Wed, Feb 22, 2017 at 4:31 AM, Sricharan wrote:
> Hi Rob,
>
>>diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
>>b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
>>new file mode 100644
>>index 000..78a8d65
>>--- /dev/null
>>+++
On Tue, Feb 14, 2017 at 1:46 PM, Robin Murphy <robin.mur...@arm.com> wrote:
> Hi Rob,
>
> On 10/02/17 18:41, Rob Clark wrote:
>> For devices with iommu(s) in secure mode, we cannot touch global
>> registers, and we have to live with the context -> sid mapping that
ether this is the best way forward, vs introducing a seperate iommu
driver, and any suggestions anyone might have. And any ideas about how
to best handle the secure context banks, since I think we have no
choice but to use them for venus (the video enc/dec block).
Signed-off-by: Rob Clark <rob
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
drivers/firmware/qcom_scm-32.c | 6 ++
drivers/firmware/qcom_scm-64.c | 16
drivers/firmware/qcom_scm.c| 6 ++
drivers/firmware/qcom_scm.h| 5 +
include/linux/qcom_scm.h | 2 ++
5 files chang
An iommu driver for Qualcomm "B" family devices which do not completely
implement the ARM SMMU spec. These devices have context-bank register
layout that is similar to ARM SMMU, but no global register space (or at
least not one that is accessible).
Signed-off-by: Rob Clark <robdcl
I want to re-use some of these for qcom_iommu, which has (roughly) the
same context-bank registers.
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
drivers/iommu/arm-smmu-regs.h | 225 ++
drivers/iommu/arm-smmu.c
From: Stanimir Varbanov <stanimir.varba...@linaro.org>
Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org>
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 28
1 file changed, 28 insertions(+)
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 68a8e67..b0daf39 100644
--- a/arch/arm6
An iommu driver for Qualcomm "B" family devices which do not completely
implement the ARM SMMU spec. These devices have context-bank register
layout that is similar to ARM SMMU, but no global register space (or at
least not one that is accessible).
Signed-off-by: Rob Clark <robdcl
From: Stanimir Varbanov <stanimir.varba...@linaro.org>
Those two new SCM calls are needed from qcom-iommu driver in order
to initialize secure iommu page table.
Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org>
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
of some in-flight patches to support IOMMU
probe deferral. You can find full branch on top of linux-next here:
git://people.freedesktop.org/~robclark/linux
next-20170228-db410c-qcom-smmu-3-venus
or github if you prefer:
https://github.com/freedreno/kernel-msm/commits/next-20170228-db410c-qco
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
drivers/firmware/qcom_scm-32.c | 6 ++
drivers/firmware/qcom_scm-64.c | 16
drivers/firmware/qcom_scm.c| 6 ++
drivers/firmware/qcom_scm.h| 5 +
include/linux/qcom_scm.h | 2 ++
5 files chang
From: Stanimir Varbanov <stanimir.varba...@linaro.org>
This bassicaly get the secure page table size, allocate memory
and return back the physical address to the trusted zone.
Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org>
Signed-off-by: Rob Clark <robd
I want to re-use some of these for qcom_iommu, which has (roughly) the
same context-bank registers.
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
drivers/iommu/arm-smmu-regs.h | 225 ++
drivers/iommu/arm-smmu.c
Cc: devicet...@vger.kernel.org
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
.../devicetree/bindings/iommu/qcom,iommu.txt | 106 +
1 file changed, 106 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iommu/qcom,iommu.txt
diff
On Wed, Mar 1, 2017 at 6:54 PM, Stephen Boyd <sb...@codeaurora.org> wrote:
> On 03/01/2017 09:42 AM, Rob Clark wrote:
>> diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c
>> new file mode 100644
>> index 000..5d3bb63
>> --- /dev/null
&g
On Wed, Jan 11, 2017 at 4:36 AM, Will Deacon <will.dea...@arm.com> wrote:
> On Tue, Jan 10, 2017 at 02:20:13PM -0500, Rob Clark wrote:
>> On Tue, Jan 10, 2017 at 12:52 PM, Will Deacon <will.dea...@arm.com> wrote:
>> > On Fri, Jan 06, 2017 at 11:26:49AM -0500, Rob C
On Tue, Jan 10, 2017 at 12:52 PM, Will Deacon <will.dea...@arm.com> wrote:
> Hi Rob,
>
> On Fri, Jan 06, 2017 at 11:26:49AM -0500, Rob Clark wrote:
>> On Thu, Jan 5, 2017 at 10:49 AM, Will Deacon <will.dea...@arm.com> wrote:
>> > On Thu, Jan 05, 2017 at 10:27:27
On Thu, Jan 5, 2017 at 6:55 AM, Will Deacon <will.dea...@arm.com> wrote:
> On Tue, Jan 03, 2017 at 04:30:54PM -0500, Rob Clark wrote:
>> TODO maybe we want two options, one to enable stalling, and 2nd to punt
>> handling to wq? I haven't needed to use mm APIs from fault han
On Wed, Jan 4, 2017 at 8:33 AM, Sricharan <sricha...@codeaurora.org> wrote:
> Hi,
>
>>-Original Message-
>>From: linux-arm-msm-ow...@vger.kernel.org
>>[mailto:linux-arm-msm-ow...@vger.kernel.org] On Behalf Of Jordan Crouse
>>Sent: Wednesday, Janu
information otherwise. Threaded handling probably only useful
with stalling, but inverse may not always be true.
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
.../devicetree/bindings/iommu/arm,smmu.txt | 3 ++
drivers/iommu/arm-smmu.c
ve my rate-
limited prints from drm/msm, since they contain additional information
about gpu state for debugging the fault.)
Rob Clark (3):
iommu/arm-smmu: Add support to opt-in to stalling
iommu/arm-smmu: Add qcom implementation
iommu/arm-smmu: Let fault handler return -EFAULT
.../devicetre
Let the iommu user ask the iommu to terminate the transaction without
printing any error msg via -EFAULT return.
(Alternatively, look for -ENOSYS return instead to trigger the msg?)
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
drivers/iommu/arm-smmu.c | 12 ++--
1 file chang
At least on the db820c I have, with the firmware I have, I'm not seeing
the SS bit set, even though the iommu is in a stalled state. So for
this implementation ignore not having SS bit set.
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
drivers/iommu/arm-smmu.c | 6 ++
1 file chan
On Wed, Jan 4, 2017 at 9:31 AM, Rob Clark <robdcl...@gmail.com> wrote:
> On Wed, Jan 4, 2017 at 8:33 AM, Sricharan <sricha...@codeaurora.org> wrote:
>> Hi,
>>
>>>-Original Message-
>>>From: linux-arm-msm-ow...@vger.kernel.org
>>>
On Thu, Jan 5, 2017 at 10:49 AM, Will Deacon <will.dea...@arm.com> wrote:
> On Thu, Jan 05, 2017 at 10:27:27AM -0500, Rob Clark wrote:
>> On Thu, Jan 5, 2017 at 6:55 AM, Will Deacon <will.dea...@arm.com> wrote:
>> > On Tue, Jan 03, 2017 at 04:30:54PM -0500, Rob Cl
On Thu, Jan 5, 2017 at 12:25 PM, Will Deacon wrote:
>> That's still got to be a per-master property, not a SMMU property, I
>> think. To illustrate:
>>
>> [A] [B] [C]
>>| |_|
>> __|__|___
>> | TBU || TBU |
>> |_| SMMU
On Thu, Aug 18, 2016 at 9:05 AM, Will Deacon wrote:
> Enabling stalling faults can result in hardware deadlock on poorly
> designed systems, particularly those with a PCI root complex upstream of
> the SMMU.
>
> Although it's not really Linux's job to save hardware
On Thu, Mar 23, 2017 at 6:21 PM, Rob Herring <r...@kernel.org> wrote:
> On Tue, Mar 14, 2017 at 11:18:05AM -0400, Rob Clark wrote:
>> Cc: devicet...@vger.kernel.org
>> Signed-off-by: Rob Clark <robdcl...@gmail.com>
>> ---
>> .../devicetree/bi
On Thu, Mar 30, 2017 at 2:19 AM, Archit Taneja <arch...@codeaurora.org> wrote:
> Hi,
>
> On 03/14/2017 08:48 PM, Rob Clark wrote:
>>
>> An iommu driver for Qualcomm "B" family devices which do not completely
>> implement the ARM SMMU spec. These d
On Mon, Mar 20, 2017 at 10:21 AM, Sricharan R <sricha...@codeaurora.org> wrote:
> Hi Rob,
>
> sorry for the delayed response. Was not there mostly last week.
>
>
> On 3/13/2017 11:49 PM, Rob Clark wrote:
>>
>> On Mon, Mar 13, 2017 at 9:38 AM, <sricha..
On Thu, Mar 9, 2017 at 10:35 AM, Sricharan R wrote:
> The MMU400x/500 is the implementation of the SMMUv2
> arch specification. It is split in to two blocks
> TBU, TCU. TBU caches the page table, instantiated
> for each master locally, clocked by the TBUn_clk.
> TCU
On Fri, Mar 31, 2017 at 1:54 PM, Will Deacon wrote:
> On Thu, Mar 09, 2017 at 09:05:43PM +0530, Sricharan R wrote:
>> This series provides the support for turning on the arm-smmu's
>> clocks/power domains using runtime pm. This is done using the
>> recently introduced device
On Fri, Mar 3, 2017 at 1:21 AM, Rob Herring <r...@kernel.org> wrote:
> On Wed, Mar 01, 2017 at 12:42:52PM -0500, Rob Clark wrote:
>
> Nit: use "dt-bindings: iommu: ..." for subject. And a commit message
> would be nice.
>
>> Cc: devicet...@vger.kernel.or
From: Stanimir Varbanov <stanimir.varba...@linaro.org>
Those two new SCM calls are needed from qcom-iommu driver in order
to initialize secure iommu page table.
Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org>
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
b410c-qcom-smmu-3-venus
or github if you prefer:
https://github.com/freedreno/kernel-msm/commits/next-20170307-db410c-qcom-smmu-3-venus
Compared to previous patchset, there have been some (mostly binding related)
cleanups. Also fixed some other-config related build issues that kbuild
robot spo
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
drivers/firmware/qcom_scm-32.c | 6 ++
drivers/firmware/qcom_scm-64.c | 16
drivers/firmware/qcom_scm.c| 6 ++
drivers/firmware/qcom_scm.h| 5 +
include/linux/qcom_scm.h | 2 ++
5 files chang
From: Stanimir Varbanov <stanimir.varba...@linaro.org>
This basically gets the secure page table size, allocates memory for
secure pagetables and passes the physical address to the trusted zone.
Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org>
Signed-off-by: Rob C
An iommu driver for Qualcomm "B" family devices which do not completely
implement the ARM SMMU spec. These devices have context-bank register
layout that is similar to ARM SMMU, but no global register space (or at
least not one that is accessible).
Signed-off-by: Rob Clark <robdcl
On Mon, Mar 13, 2017 at 9:38 AM, wrote:
> Hi Rob,
>
> [..]
>
>
>> +static int qcom_iommu_init_domain(struct iommu_domain *domain,
>> + struct qcom_iommu_dev *qcom_iommu,
>> + struct iommu_fwspec *fwspec)
>>
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 68a8e67..b0daf39 100644
--- a/arch/arm6
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 57 +++
1 file changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 7bcf4cd..8aeec6f 100644
---
From: Stanimir Varbanov <stanimir.varba...@linaro.org>
Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org>
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 28
1 file changed, 28 insertions(+)
I want to re-use some of these for qcom_iommu, which has (roughly) the
same context-bank registers.
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
drivers/iommu/arm-smmu-regs.h | 225 ++
drivers/iommu/arm-smmu.c
On Tue, Mar 7, 2017 at 12:48 PM, Robin Murphy <robin.mur...@arm.com> wrote:
> On 01/03/17 17:42, Rob Clark wrote:
>> An iommu driver for Qualcomm "B" family devices which do not completely
>> implement the ARM SMMU spec.
>
> Is that actually true, or is it jus
e that all the dependencies for this driver have been merged
since 4.12, and it is the last thing needed for having another fully-
enabled (gpu/display/video codec/etc) ARM device that is fully upstream.
One minor change to move a couple #defines and MMU500 bits back to
arm-smmu.c as suggested by
devicetree instead of setting it up dynamically.
In the end, other than register definitions, there is not much code to
share with arm-smmu (other than what has already been refactored out
into the pgtable helpers).
Signed-off-by: Rob Clark <robdcl...@gmail.com>
Tested-by: Riku
From: Stanimir Varbanov <stanimir.varba...@linaro.org>
This basically gets the secure page table size, allocates memory for
secure pagetables and passes the physical address to the trusted zone.
Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org>
Signed-off-by: Rob C
Cc: devicet...@vger.kernel.org
Signed-off-by: Rob Clark <robdcl...@gmail.com>
Reviewed-by: Rob Herring <r...@kernel.org>
Tested-by: Archit Taneja <arch...@codeaurora.org>
---
.../devicetree/bindings/iommu/qcom,iommu.txt | 121 +
1 file changed, 121 ins
I want to re-use some of these for qcom_iommu, which has (roughly) the
same context-bank registers.
Signed-off-by: Rob Clark <robdcl...@gmail.com>
Tested-by: Archit Taneja <arch...@codeaurora.org>
---
drivers/iommu/arm-smmu-regs.h | 220 ++
d
On Tue, Aug 15, 2017 at 11:42 AM, Joerg Roedel <j...@8bytes.org> wrote:
> On Sun, Aug 13, 2017 at 10:27:36AM -0400, Rob Clark wrote:
>> Hi Joerg,
>>
>> These patches have been on list for quite some time now. The bindings
>> have r-b from Rob Herring, and the p
Add maintainer entry for qcom_iommu.
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 44cb004c765d..8e6ab3d2e01f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10941,6 +10941,13 @@ T:
in the git repository at:
git://people.freedesktop.org/~robclark/linux
for you to fetch changes up to 8a4342ede167b8c095961846e908b9ac1c884650:
iommu: qcom: initialize secure page table (2017-08-12 11:50:35 -0400)
Rob Clark (3
On Sun, Aug 13, 2017 at 10:27 AM, Rob Clark <robdcl...@gmail.com> wrote:
> Hi Joerg,
>
> These patches have been on list for quite some time now. The bindings
> have r-b from Rob Herring, and the patch touching arm-smmu has Will's
> a-b. And all the review comments on th
On Thu, Jul 13, 2017 at 9:53 AM, Sricharan R <sricha...@codeaurora.org> wrote:
> Hi,
>
> On 7/13/2017 5:20 PM, Rob Clark wrote:
>> On Thu, Jul 13, 2017 at 1:35 AM, Sricharan R <sricha...@codeaurora.org>
>> wrote:
>>> Hi Vivek,
>>>
>>>
On Thu, Jul 13, 2017 at 5:50 AM, Robin Murphy wrote:
> On 13/07/17 07:48, Stephen Boyd wrote:
>> On 07/13, Vivek Gautam wrote:
>>> Hi Stephen,
>>>
>>>
>>> On 07/13/2017 04:24 AM, Stephen Boyd wrote:
On 07/06, Vivek Gautam wrote:
> @@ -1231,12 +1237,18 @@ static int
devicetree instead of setting it up dynamically.
In the end, other than register definitions, there is not much code to
share with arm-smmu (other than what has already been refactored out
into the pgtable helpers).
Signed-off-by: Rob Clark <robdcl...@gmail.com>
Tested-by: Riku
I want to re-use some of these for qcom_iommu, which has (roughly) the
same context-bank registers.
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
drivers/iommu/arm-smmu-regs.h | 227 ++
drivers/iommu/arm-smmu.c
Cc: devicet...@vger.kernel.org
Signed-off-by: Rob Clark <robdcl...@gmail.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
.../devicetree/bindings/iommu/qcom,iommu.txt | 121 +
1 file changed, 121 insertions(+)
create mode 100644 Documentation/devicet
From: Stanimir Varbanov <stanimir.varba...@linaro.org>
This basically gets the secure page table size, allocates memory for
secure pagetables and passes the physical address to the trusted zone.
Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org>
Signed-off-by: Rob C
e that all the dependencies for this driver have been merged
since 4.12, and it is the last thing needed for having another fully-
enabled (gpu/display/video codec/etc) ARM device that is fully upstream.
Rob Clark (3):
Docs: dt: document qcom iommu bindings
iommu: arm-smmu: split out regist
On Thu, Jul 13, 2017 at 1:35 AM, Sricharan R wrote:
> Hi Vivek,
>
> On 7/13/2017 10:43 AM, Vivek Gautam wrote:
>> Hi Stephen,
>>
>>
>> On 07/13/2017 04:24 AM, Stephen Boyd wrote:
>>> On 07/06, Vivek Gautam wrote:
@@ -1231,12 +1237,18 @@ static int
On Thu, Jul 13, 2017 at 8:02 AM, Marek Szyprowski
<m.szyprow...@samsung.com> wrote:
> Hi All,
>
> On 2017-07-13 13:50, Rob Clark wrote:
>>
>> On Thu, Jul 13, 2017 at 1:35 AM, Sricharan R <sricha...@codeaurora.org>
>> wrote:
>>>
>>> On 7/13/2
On Fri, Jul 14, 2017 at 2:06 PM, Will Deacon <will.dea...@arm.com> wrote:
> On Fri, Jul 14, 2017 at 01:42:13PM -0400, Rob Clark wrote:
>> On Fri, Jul 14, 2017 at 1:07 PM, Will Deacon <will.dea...@arm.com> wrote:
>> > On Thu, Jul 13, 2017 at 10:55:10AM -0400, Rob Cla
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