es in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> Documentation/devicetree/bindings/iommu/rockchip,iommu.txt | 7 +++
> 1 file changed, 7 insertions(+)
Reviewed-by: Rob Herring
On Wed, Mar 7, 2018 at 12:32 AM, Vivek Gautam
wrote:
> Qualcomm's arm-smmu 500 implementation supports runtime pm
> so enable the same.
That's a driver detail unrelated to the binding.
>
> Signed-off-by: Vivek Gautam
> ---
>
> Based on iommu/arm-smmu pm runtime support series [1]:
> [PATCH v8
On Mon, Mar 05, 2018 at 07:59:21PM +0530, Nipun Gupta wrote:
> The existing IOMMU bindings cannot be used to specify the relationship
> between fsl-mc devices and IOMMUs. This patch adds a binding for
> mapping fsl-mc devices to IOMMUs, using a new iommu-parent property.
>
> Signed-off-by: Nipun G
On Fri, Mar 23, 2018 at 03:38:09PM +0800, Jeffy Chen wrote:
> Add clock property, since we are going to control clocks in rockchip
> iommu driver.
>
> Signed-off-by: Jeffy Chen
> Reviewed-by: Robin Murphy
> ---
Reviewed-by: Rob Herring
___
; Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt |1 +
> 1 file changed, 1 insertion(+)
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On Fri, Mar 16, 2018 at 8:51 AM, Geert Uytterhoeven
wrote:
> Hi all,
>
> If NO_DMA=y, get_dma_ops() returns a reference to the non-existing
> symbol bad_dma_ops, thus causing a link failure if it is ever used.
>
> The intention of this is twofold:
> 1. To catch users of the DMA API on sy
++---
> drivers/of/device.c | 6 --
> drivers/of/of_reserved_mem.c | 2 +-
> drivers/pci/pci-driver.c | 3 +--
> include/linux/device.h| 4
> include/linux/of_device.h | 8 ++++++--
> 10 files changed, 17 insertions(+), 19 deletions(-)
Reviewed-by:
On Tue, Apr 10, 2018 at 01:26:41PM +0200, Heiko Stuebner wrote:
> Hi Robin,
>
> Am Dienstag, 10. April 2018, 13:18:48 CEST schrieb Robin Murphy:
> > On 10/04/18 10:26, Heiko Stuebner wrote:
> > > Rockchip IOMMUs are used without explicit clock handling for 4 years
> > > now, so we should keep comp
Similar to the single handle drm_gem_object_lookup(),
drm_gem_objects_lookup() takes an array of handles and returns an array
of GEM objects.
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Sean Paul
Cc: David Airlie
Cc: Daniel Vetter
Signed-off-by: Rob Herring
---
drivers/gpu/drm/drm_gem.c
org
Signed-off-by: Rob Herring
---
Please ack this as I need to apply it to the drm-misc tree. Or we need a
stable branch with this patch.
v3:
- Rework arm_lpae_prot_to_pte as written by Robin
- Fill in complete register values for TRANSTAB and MEMATTR registers
drivers/iommu/io-pgtable-
e via
drm-misc or we need a stable branch.
A git branch is here[1].
Rob
[1] git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git
panfrost-rebase-v2
Rob Herring (3):
iommu: io-pgtable: Add ARM Mali midgard MMU page table format
drm: Add a drm_gem_objects_lookup helper
drm/panfrost
On Mon, Apr 1, 2019 at 8:07 AM Daniel Vetter wrote:
>
> On Mon, Apr 1, 2019 at 9:47 AM Rob Herring wrote:
> >
> > Similar to the single handle drm_gem_object_lookup(),
> > drm_gem_objects_lookup() takes an array of handles and returns an array
> > of GEM objects.
On Mon, Apr 1, 2019 at 2:12 PM Robin Murphy wrote:
>
> On 01/04/2019 08:47, Rob Herring wrote:
> > This adds the initial driver for panfrost which supports Arm Mali
> > Midgard and Bifrost family of GPUs. Currently, only the T860 and
> > T760 Midgard GPUs have been tested.
On Mon, Apr 1, 2019 at 10:43 AM Eric Anholt wrote:
>
> Chris Wilson writes:
>
> > Quoting Daniel Vetter (2019-04-01 14:06:48)
> >> On Mon, Apr 1, 2019 at 9:47 AM Rob Herring wrote:
> >> > +{
> >> > + int i, re
On Fri, Apr 5, 2019 at 7:30 AM Steven Price wrote:
>
> On 01/04/2019 08:47, Rob Herring wrote:
> > This adds the initial driver for panfrost which supports Arm Mali
> > Midgard and Bifrost family of GPUs. Currently, only the T860 and
> > T760 Midgard GPUs have been tested
On Tue, Apr 9, 2019 at 10:56 AM Tomeu Vizoso wrote:
>
> On Mon, 8 Apr 2019 at 23:04, Rob Herring wrote:
> >
> > On Fri, Apr 5, 2019 at 7:30 AM Steven Price wrote:
> > >
> > > On 01/04/2019 08:47, Rob Herring wrote:
> > > > This adds the ini
fore -rc5 cutoff.
A git branch is here[1].
Rob
[1] git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git
panfrost-rebase-v3
Rob Herring (3):
iommu: io-pgtable: Add ARM Mali midgard MMU page table format
drm: Add a drm_gem_objects_lookup helper
drm/panfrost: Add initial panfrost
dation.org
Acked-by: Alyssa Rosenzweig
Signed-off-by: Rob Herring
---
This is really v4 of the patch. v3 is the series version.
Joerg, please ack so we can take this via the drm tree.
v3:
- Incorporated refactoring from Robin
drivers/iommu/io-pgtable-arm.c | 91 ++---
On Fri, May 17, 2019 at 1:47 PM Clément Péron wrote:
>
> Allwinner H6 has an ARM Mali-T720 MP2 which required a bus_clock.
>
> Add an optional bus_clock at the init of the panfrost driver.
>
> Signed-off-by: Clément Péron
> ---
> drivers/gpu/drm/panfrost/panfrost_device.c | 25 ++
On Fri, May 17, 2019 at 1:48 PM Isaac J. Manjarres
wrote:
>
> Kernel modules may want to use of_phandle_iterator_args(),
> so export it.
>
> Signed-off-by: Isaac J. Manjarres
> ---
> drivers/of/base.c | 1 +
> 1 file changed, 1 insertion(+
On Fri, May 17, 2019 at 5:08 PM Clément Péron wrote:
>
> Hi Rob,
>
> On Fri, 17 May 2019 at 22:07, Rob Herring wrote:
> >
> > On Fri, May 17, 2019 at 1:47 PM Clément Péron wrote:
> > >
> > > Allwinner H6 has an ARM Mali-T720 MP2 which required a bus_cl
.
>
> I'm pushing it in case someone want to continue the work.
>
> This has been tested with Mesa3D 19.1.0-RC2 and a GPU bitness patch[1].
>
> One patch is from Icenowy Zheng where I changed the order as required
> by Rob Herring[2].
>
> Thanks,
> Clem
On Wed, May 22, 2019 at 2:41 PM Clément Péron wrote:
>
> Hi Rob,
>
> On Wed, 22 May 2019 at 21:27, Rob Herring wrote:
> >
> > On Tue, May 21, 2019 at 11:11 AM Clément Péron wrote:
> > >
> > > Hi,
> > >
> > > The Allwinner H6 ha
e/dd.c| 19 ++-
> drivers/base/power/domain.c | 2 +-
> drivers/iommu/of_iommu.c | 2 +-
> drivers/pinctrl/devicetree.c | 9 +
> include/linux/device.h | 18 +-
> 5 files changed, 38 insertions(+), 12 deletions(-)
Acked-by: Rob Herring
tation/{crc32.txt => crc32.rst}| 2 +
> Documentation/{dcdbas.txt => dcdbas.rst} | 2 +
> ...ging-modules.txt => debugging-modules.rst} | 2 +
> ...hci1394.txt => debugging-via-ohci1394.rst} | 2 +
> Documentation/{dell_rbu.txt => dell_rbu.rst}
Roedel
Cc: linux-arm-ker...@lists.infradead.org
Cc: iommu@lists.linux-foundation.org
Signed-off-by: Rob Herring
---
This is needed for large (up to 1GB AIUI) scratch buffers on panfrost
which are mapped on demand on GPU page faults and can be unmapped on
memory pressure. Alternatively, I'd
On Thu, Jul 11, 2019 at 4:23 AM Will Deacon wrote:
>
> On Wed, Jul 10, 2019 at 04:31:19PM -0600, Rob Herring wrote:
> > If a region has been mapped sparsely (such as on page faults), the user
> > has to keep track of what was mapped or not in order to avoid warnings
> > w
implementation of Marvell, this compatible is used for errata only.
>
> Signed-off-by: Hanna Hawa
> Signed-off-by: Gregory CLEMENT
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Rob Herring
On Wed, Jul 31, 2019 at 9:48 AM Nicolas Saenz Julienne
wrote:
>
> Some SoCs might have multiple interconnects each with their own DMA
> addressing limitations. This function parses the 'dma-ranges' on each of
> them and tries to guess the maximum SoC wide DMA addressable memory
> size.
>
> This is
On Mon, Aug 5, 2019 at 10:03 AM Nicolas Saenz Julienne
wrote:
>
> Hi Rob,
> Thanks for the review!
>
> On Fri, 2019-08-02 at 11:17 -0600, Rob Herring wrote:
> > On Wed, Jul 31, 2019 at 9:48 AM Nicolas Saenz Julienne
> > wrote:
> > > Some SoCs might have multip
On Tue, Aug 6, 2019 at 12:12 PM Nicolas Saenz Julienne
wrote:
>
> Hi Rob,
>
> On Mon, 2019-08-05 at 13:23 -0600, Rob Herring wrote:
> > On Mon, Aug 5, 2019 at 10:03 AM Nicolas Saenz Julienne
> > wrote:
> > > Hi Rob,
> > > Thanks for the review!
> >
d parameter,
> leaving current functionality unchanged.
>
> Signed-off-by: Lorenzo Pieralisi
> Cc: Rob Herring
> Cc: Robin Murphy
> Cc: Joerg Roedel
> Cc: Laurentiu Tudor
> ---
> drivers/bus/fsl-mc/fsl-mc-bus.c | 4 +-
> drivers/iommu/of_iommu.c| 81 +
an input parameter.
>
> Signed-off-by: Diana Craciun
> Signed-off-by: Lorenzo Pieralisi
> Acked-by: Bjorn Helgaas# pci/msi.c
> Cc: Bjorn Helgaas
> Cc: Rob Herring
> Cc: Marc Zyngier
> ---
> drivers/of/irq.c | 8 +---
> drivers/pci/msi.c | 2 +-
>
operty.
> In addition, deprecate msi-parent property which no longer makes sense
> now that we support translating the MSIs.
>
> Signed-off-by: Laurentiu Tudor
> Signed-off-by: Diana Craciun
> Cc: Rob Herring
> ---
> .../devicetree/bindings/misc/fsl,qoriq-mc.txt |
all busses that require
> input/output ID translations.
>
> No functional change intended.
>
> Signed-off-by: Lorenzo Pieralisi
> Cc: Bjorn Helgaas
> Cc: Rob Herring
> Cc: Marc Zyngier
> ---
> drivers/of/irq.c | 28 ++--
> drivers/
On Tue, Jul 07, 2020 at 10:00:16PM -0700, Krishna Reddy wrote:
> Add binding for NVIDIA's Tegra194 SoC SMMU.
>
> Signed-off-by: Krishna Reddy
> ---
> .../devicetree/bindings/iommu/arm,smmu.yaml| 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git a/Documentation/devicet
gt; > + - enum:
> > > + - marvell,ap806-smmu-500
> >
> > Isn't a single-valued enum just a constant? :P
>
> That's how copy-paste engineering ends up :)
It's fine like this if you expect more SoCs to be added.
Either way,
Reviewed-by: Rob Herring
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e RID instances/names to a generic "id" tag.
>
> No functionality change intended.
>
> Signed-off-by: Lorenzo Pieralisi
> Cc: Rob Herring
> Cc: Joerg Roedel
> Cc: Robin Murphy
> Cc: Marc Zyngier
> ---
> drivers/iomm
On Mon, Jul 13, 2020 at 8:10 AM Robin Murphy wrote:
>
> On 2020-07-10 21:29, Krishna Reddy wrote:
> > Thanks Rob. One question on setting "minItems: ". Please see below.
> >
> >>> +allOf:
> >>> + - if:
> >>> + properties:
> >>> +compatible:
> >>> + contains:
> >>> +
On Thu, Jul 02, 2020 at 05:37:17PM +0800, Miles Chen wrote:
> Add a description for mediatek,infracfg. We can check if 4GB mode
> is enable by reading it instead of checking the unexported
> symbol "max_pfn".
>
> This is a step towards building mtk_iommu as a kernel module.
You determined this be
eletions(-)
> create mode 100644 include/dt-bindings/memory/mtk-smi-larb-port.h
>
Acked-by: Rob Herring
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On Sat, 11 Jul 2020 14:48:27 +0800, Yong Wu wrote:
> Extend the max larb number definition as mt8192 has larb_nr over 16.
>
> Signed-off-by: Yong Wu
> ---
> include/dt-bindings/memory/mtk-smi-larb-port.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
On Sat, Jul 11, 2020 at 02:48:29PM +0800, Yong Wu wrote:
> This patch adds decriptions for mt8192 IOMMU and SMI.
>
> mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation
> table format. The M4U-SMI HW diagram is as below:
>
> EMI
>
renesas/r8a774e1.dtsi | 121 ++
> 1 file changed, 121 insertions(+)
Acked-by: Rob Herring
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On Mon, Jul 13, 2020 at 10:35:12PM +0100, Lad Prabhakar wrote:
> Document RZ/G2H (R8A774E1) SoC bindings.
>
> Signed-off-by: Lad Prabhakar
> ---
> Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml | 1 +
> 1 file changed, 1 insertion(+)
Ack
as,ravb.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring
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changed, 1 insertion(+)
>
Acked-by: Rob Herring
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On Sat, Jul 11, 2020 at 02:48:43PM +0800, Yong Wu wrote:
> Some HW IP(ex: CCU) require the special iova range. That means the
> iova got from dma_alloc_attrs for that devices must locate in his
> special range. In this patch, we allocate a special iova_range for
> each a special requirement and cre
On Fri, Jul 24, 2020 at 2:45 PM Jim Quinlan wrote:
>
> The new field 'dma_range_map' in struct device is used to facilitate the
> use of single or multiple offsets between mapping regions of cpu addrs and
> dma addrs. It subsumes the role of "dev->dma_pfn_offset" which was only
> capable of holdi
On Wed, Jul 29, 2020 at 12:19 AM Christoph Hellwig wrote:
>
> On Tue, Jul 28, 2020 at 02:24:51PM -0400, Jim Quinlan wrote:
> > I started using devm_kcalloc() but at least two reviewers convinced me
> > to just use kcalloc(). In addition, when I was using devm_kcalloc()
> > it was awkward because
On Thu, Jul 30, 2020 at 10:44 AM Jim Quinlan wrote:
>
> On Wed, Jul 29, 2020 at 10:28 AM Rob Herring wrote:
> >
> > On Wed, Jul 29, 2020 at 12:19 AM Christoph Hellwig wrote:
> > >
> > > On Tue, Jul 28, 2020 at 02:24:51PM -0400, Jim Quinlan wrote:
> >
On Tue, Jul 28, 2020 at 01:01:39PM +0800, Claire Chang wrote:
> Introduce the new compatible string, device-swiotlb-pool, for restricted
> DMA. One can specify the address and length of the device swiotlb memory
> region by device-swiotlb-pool in the device tree.
>
> Signed-off-by: Claire Chang
>
ion(+), 1 deletion(-)
>
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On Wed, Mar 23, 2022 at 5:15 PM dann frazier wrote:
>
> On Wed, Mar 23, 2022 at 09:49:04AM +, Marc Zyngier wrote:
> > On Tue, 22 Mar 2022 17:27:36 +,
> > Robin Murphy wrote:
> > >
> > > Originally, creating the dma_ranges resource list in pre-sorted fashion
> > > was the simplest and most
On Tue, Mar 22, 2022 at 12:27 PM Robin Murphy wrote:
>
> Originally, creating the dma_ranges resource list in pre-sorted fashion
> was the simplest and most efficient way to enforce the order required by
> iova_reserve_pci_windows(). However since then at least one PCI host
> driver is now re-sort
There's no need to show consumer side in provider examples. The ones
used here are undocumented or undocumented in schemas which results in
warnings.
Signed-off-by: Rob Herring
---
.../devicetree/bindings/iommu/mediatek,iommu.yaml | 10 --
.../devicetree/bindings/iommu/sa
dings/mmc/sdhci-msm.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
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time and just build the list in whatever natural order the DT had.
>
> Signed-off-by: Robin Murphy
> ---
>
> v2: Clean up now-unused local variable
>
> drivers/iommu/dma-iommu.c | 13 -
> drivers/pci/of.c | 8 +---
> 2 files changed,
On Thu, 12 May 2022 21:00:48 +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> This adds the "iommu-addresses" property to reserved-memory nodes, which
> allow describing the interaction of memory regions with IOMMUs. Two use-
> cases are supported:
>
> 1. Static mappings can be describe
On Fri, Apr 29, 2022 at 5:09 PM Saravana Kannan wrote:
>
> The deferred probe timer that's used for this currently starts at
> late_initcall and runs for driver_deferred_probe_timeout seconds. The
> assumption being that all available drivers would be loaded and
> registered before the timer expir
On Fri, May 13, 2022 at 12:26 PM Saravana Kannan wrote:
>
> On Fri, May 13, 2022 at 6:58 AM Rob Herring wrote:
> >
> > On Fri, Apr 29, 2022 at 5:09 PM Saravana Kannan
> > wrote:
> > >
> > > The deferred probe timer that's used for this curre
6795-larb-port.h | 96 +++
> 2 files changed, 99 insertions(+)
> create mode 100644 include/dt-bindings/memory/mt6795-larb-port.h
>
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> v3:
> * New patch
> v4:
> * Remove memory-contexts subnode.
> ---
> .../bindings/display/tegra/nvidia,tegra20-host1x.yaml| 5 +
> 1 file changed, 5 insertions(+)
>
Acked-by: Rob Herring
___
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ee.
Wait, what? If there's only one possible node that can match, I prefer
the 'old way'. Until we implemented a phandle cache, searching the
entire tree was how phandle lookups worked too, so not any better.
But if this makes things more consistent
iommu node in upstream mt8195 devicetrees
> yet.
>
> .../devicetree/bindings/iommu/mediatek,iommu.yaml | 10 ++
> 1 file changed, 10 insertions(+)
>
Acked-by: Rob Herring
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On Wed, May 18, 2022 at 10:14:43AM +0200, AngeloGioacchino Del Regno wrote:
> Il 18/05/22 03:41, Rob Herring ha scritto:
> > On Tue, May 17, 2022 at 03:21:06PM +0200, AngeloGioacchino Del Regno wrote:
> > > Both MT2712 and MT8173 got a mediatek,infracfg phandle: add that to
On Wed, May 18, 2022 at 12:07:58PM +0100, Robin Murphy wrote:
> On 2022-05-18 09:29, AngeloGioacchino Del Regno wrote:
> > Il 17/05/22 16:12, Robin Murphy ha scritto:
> > > On 2022-05-17 14:21, AngeloGioacchino Del Regno wrote:
> > > > This driver will get support for more SoCs and the list of infr
6795-larb-port.h | 96 +++
> 2 files changed, 100 insertions(+)
> create mode 100644 include/dt-bindings/memory/mt6795-larb-port.h
>
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On Wed, May 18, 2022 at 01:42:20PM +0200, AngeloGioacchino Del Regno wrote:
> Il 18/05/22 13:29, Matthias Brugger ha scritto:
> >
> >
> > On 18/05/2022 12:04, AngeloGioacchino Del Regno wrote:
> > > Add properties "mediatek,infracfg" and "mediatek,pericfg" to let the
> > > mtk_iommu driver retrie
On Wed, May 25, 2022 at 10:31:46AM +0900, Nobuhiro Iwamatsu wrote:
> Add documentation for the binding of Toshiba Visconti5 SoC's IOMMU.
>
> Signed-off-by: Nobuhiro Iwamatsu
> ---
> .../bindings/iommu/toshiba,visconti-atu.yaml | 62 +++
> 1 file changed, 62 insertions(+)
> crea
On Fri, May 27, 2022 at 11:28:59PM +0200, Konrad Dybcio wrote:
> From: AngeloGioacchino Del Regno
>
> Some IOMMUs associated with some TZ firmwares may support switching
> to the AArch64 pagetable format by sending a "set pagetable format"
> scm command indicating the IOMMU secure ID and the cont
On Mon, May 30, 2022 at 08:03:26PM +0200, Fabien Parent wrote:
> Add IOMMU binding documentation for the MT8365 SoC.
>
> Signed-off-by: Fabien Parent
> ---
> .../bindings/iommu/mediatek,iommu.yaml| 2 +
> include/dt-bindings/memory/mt8365-larb-port.h | 96 +++
> 2 files
rant DMA
> ops"
>
> Changes V3 -> V4:
>- add Stefano's R-b
>- remove underscore in iommu node name
>- remove consumer example virtio@3000
>- update text for two descriptions
> ---
> .../devicetree/bindings/iommu/xen,gr
On Thu, 09 Jun 2022 12:07:57 +0200, AngeloGioacchino Del Regno wrote:
> Add property "mediatek,infracfg" to let the mtk_iommu driver retrieve
> a phandle to the infracfg syscon instead of performing a per-soc
> compatible lookup in the entire devicetree and set it as a required
> property for MT271
d, 1 insertion(+)
>
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On Tue, 21 Jun 2022 18:10:14 +0300, Mikko Perttunen wrote:
> From: Thierry Reding
>
> Convert the Tegra host1x controller bindings from the free-form text
> format to json-schema.
>
> This also adds the missing display-hub DT bindings that were not
> previously documented.
On Fri, Jun 24, 2022 at 11:26 AM Rob Herring wrote:
>
> On Tue, 21 Jun 2022 18:10:14 +0300, Mikko Perttunen wrote:
> > From: Thierry Reding
> >
> > Convert the Tegra host1x controller bindings from the free-form text
> > format to json-schema.
> >
> >
On Thu, Jun 23, 2022 at 12:04:21PM +0200, sascha hauer wrote:
> On Thu, Jun 23, 2022 at 01:03:43AM -0700, Saravana Kannan wrote:
> > Commit 71066545b48e ("driver core: Set fw_devlink.strict=1 by default")
> > enabled iommus and dmas dependency enforcement by default. On some
> > systems, this cause
On Thu, Jun 30, 2022 at 5:11 PM Saravana Kannan wrote:
>
> On Mon, Jun 27, 2022 at 2:10 AM Tony Lindgren wrote:
> >
> > * Saravana Kannan [220623 08:17]:
> > > On Thu, Jun 23, 2022 at 12:01 AM Tony Lindgren wrote:
> > > >
> > > > * Saravana Kannan [220622 19:05]:
> > > > > On Tue, Jun 21, 2022
to know the dma_address requirements of its iommu
> consumer devices.
>
> [1]
> https://lore.kernel.org/linux-arm-kernel/5c7946f3-b56e-da00-a750-be097c7ce...@arm.com/
>
> CC: Rob Herring
> CC: Frank Rowand
> Fixes: e0d072782c73 ("dma-mapping: introduce DMA range map
On Wed, Jan 27, 2021 at 7:13 AM Robin Murphy wrote:
>
> [ + Christoph, Marek ]
>
> On 2021-01-27 13:00, Paul Kocialkowski wrote:
> > Hi,
> >
> > On Tue 19 Jan 21, 18:52, Yong Wu wrote:
> >> The commit e0d072782c73 ("dma-mapping: introduce DMA range map,
> >> supplanting dma_pfn_offset") always upd
u
> consumer devices.
>
> [1]
> https://lore.kernel.org/linux-arm-kernel/5c7946f3-b56e-da00-a750-be097c7ce...@arm.com/
>
> CC: Rob Herring
> CC: Frank Rowand
> Fixes: e0d072782c73 ("dma-mapping: introduce DMA range map, supplanting
> dma_pfn_offset"),
&
n Gen 3
which can be conditioned on !renesas,ipmmu-vmsa.
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Yoshihiro Shimoda
Cc: iommu@lists.linux-foundation.org
Signed-off-by: Rob Herring
---
.../bindings/iommu/renesas,ipmmu-vmsa.yaml | 12 +++-
1 file changed, 11 insertions(+), 1 delet
rnel.org
Cc: linux-g...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: iommu@lists.linux-foundation.org
Cc: linux-watch...@vger.kernel.org
Signed-off-by: Rob Herring
---
.../bindings/clock/allwinner,sun9i-a80-usb-clocks.yaml| 2 +-
Documentation/devicetree/bindings/clock/arm,s
od Koul
Cc: Geert Uytterhoeven
Cc: Linus Walleij
Cc: Daniel Lezcano
Cc: linux-cry...@vger.kernel.org
Cc: dri-de...@lists.freedesktop.org
Cc: linux-l...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: linux-g...@vger.kernel.org
Signed-off-by: Rob Herring
---
.../devicetree/bindings/c
On Wed, Feb 03, 2021 at 09:01:23AM +0100, Geert Uytterhoeven wrote:
> Hi Rob,
>
> On Tue, Feb 2, 2021 at 9:55 PM Rob Herring wrote:
> > Properties in if/then schemas weren't getting checked by the meta-schemas.
> > Enabling meta-schema checks finds several errors.
&g
On Tue, Feb 02, 2021 at 04:33:56PM -0800, Stephen Boyd wrote:
> Quoting Rob Herring (2021-02-02 12:55:42)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-usb-clocks.yaml
> >
> > b/Documentation/devicetree/bindings/clock/al
On Wed, Feb 03, 2021 at 05:07:26PM +0800, Chunyan Zhang wrote:
> From: Chunyan Zhang
>
> This iommu module can be used by Unisoc's multimedia devices, such as
> display, Image codec(jpeg) and a few signal processors, including
> VSP(video), GSP(graphic), ISP(image), and CPP(camera pixel processor
On Fri, Feb 5, 2021 at 1:21 AM Chunyan Zhang wrote:
>
> Hi Rob,
>
> On Fri, 5 Feb 2021 at 07:25, Rob Herring wrote:
> >
> > On Wed, Feb 03, 2021 at 05:07:26PM +0800, Chunyan Zhang wrote:
> > > From: Chunyan Zhang
> > >
> > > This iommu module
On Wed, Mar 10, 2021 at 9:08 AM Will Deacon wrote:
>
> Hi Claire,
>
> On Tue, Feb 09, 2021 at 02:21:30PM +0800, Claire Chang wrote:
> > Introduce the new compatible string, restricted-dma-pool, for restricted
> > DMA. One can specify the address and length of the restricted DMA memory
> > region b
On Sat, 20 Mar 2021 15:20:08 +, Sven Peter wrote:
> DART (Device Address Resolution Table) is the iommu found on Apple
> ARM SoCs such as the M1.
>
> Signed-off-by: Sven Peter
> ---
> .../bindings/iommu/apple,t8103-dart.yaml | 82 +++
> MAINTAINERS
On Sun, Mar 21, 2021 at 05:00:50PM +0100, Mark Kettenis wrote:
> > Date: Sat, 20 Mar 2021 15:19:33 +
> > From: Sven Peter
> >
> > Hi,
> >
> > After Hector's initial work [1] to bring up Linux on Apple's M1 it's time to
> > bring up more devices. Most peripherals connected to the SoC are behi
On Thu, Apr 22, 2021 at 02:16:53PM -0300, Ezequiel Garcia wrote:
> (Adding Kever)
>
> Hi Benjamin,
>
> Thanks a lot for working on this, it looks amazing. Together with the great
> work
> that Rockchip is doing, it seems RK3566/RK3568 will have decent support very
> soon.
>
> One comment here:
On Thu, Apr 22, 2021 at 04:16:00PM +0200, Benjamin Gaignard wrote:
> Add compatible for the second version of IOMMU hardware block.
> RK356x IOMMU can also be link to a power domain.
>
> Signed-off-by: Benjamin Gaignard
> ---
> version 2:
> - Add power-domains property
>
> .../devicetree/bindi
On Tue, May 04, 2021 at 10:41:21AM +0200, Benjamin Gaignard wrote:
> Convert Rockchip IOMMU to DT schema
>
> Signed-off-by: Benjamin Gaignard
> ---
> version 2:
> - Change maintainer
> - Change reg maxItems
> - Change interrupt maxItems
>
> .../bindings/iommu/rockchip,iommu.txt | 38
;
> version 2:
> - Add power-domains property
>
> .../devicetree/bindings/iommu/rockchip,iommu.yaml | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring
___
iommu mailing l
rtions(+), 38 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/iommu/rockchip,iommu.txt
> create mode 100644
> Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml
>
Reviewed-by: Rob Herring
___
iommu mailing list
iommu@
On Mon, May 17, 2021 at 01:17:05PM +, Wang Xingang wrote:
> From: Xingang Wang
>
> When booting with devicetree, the pci_request_acs() is called after the
> enumeration and initialization of PCI devices, thus the ACS is not
> enabled. This patch add check for IOMMU in of_core_init(), and call
On Thu, May 20, 2021 at 2:28 AM Wang Xingang wrote:
>
> From: Xingang Wang
>
> When booting with devicetree, the pci_request_acs() is called after the
> enumeration and initialization of PCI devices, thus the ACS is not
> enabled. And ACS should be enabled when IOMMU is detected for the
> PCI hos
On Fri, Apr 23, 2021 at 06:32:30PM +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> Reserved memory region phandle references can be accompanied by a
> specifier that provides additional information about how that specific
> reference should be treated.
>
> One use-case is to mark a memor
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