Re: [RFC PATCH v2 13/15] drivers: acpi: iort: introduce iort_iommu_configure

On 07.06.2016 15:31, Lorenzo Pieralisi wrote: +static int __get_pci_rid(struct pci_dev *pdev, u16 alias, void *data) +{ + u32 *rid = data; + + *rid = alias; + return 0; +} + +/** + * iort_iommu_configure - Set-up IOMMU configuration for a device. + * + * @dev: device to

Re: [RFC PATCH 09/11] drivers: acpi: implement acpi_dma_configure

On 17.05.2016 10:07, Tomasz Nowicki wrote: Hi Lorenzo, On 14.04.2016 19:25, Lorenzo Pieralisi wrote: On DT based systems, the of_dma_configure() API implements DMA configuration for a given device. On ACPI systems an API equivalent to of_dma_configure() is missing which implies

Re: [RFC PATCH 09/11] drivers: acpi: implement acpi_dma_configure

On 18.04.2016 12:43, Robin Murphy wrote: On 15/04/16 19:29, Timur Tabi wrote: On Thu, Apr 14, 2016 at 12:25 PM, Lorenzo Pieralisi wrote: +void acpi_dma_configure(struct device *dev, enum dev_dma_attr attr) +{ + struct iommu_ops *iommu; + + iommu =

Re: [RFC PATCH 09/11] drivers: acpi: implement acpi_dma_configure

On 16.05.2016 17:15, Tomasz Nowicki wrote: On 18.04.2016 12:43, Robin Murphy wrote: On 15/04/16 19:29, Timur Tabi wrote: On Thu, Apr 14, 2016 at 12:25 PM, Lorenzo Pieralisi <lorenzo.pieral...@arm.com> wrote: +void acpi_dma_configure(struct device *dev, enum dev_dma_att

Re: [PATCH V7 01/11] iommu/of: Refactor of_iommu_configure() for error handling

Hi Sricharan, On 23.01.2017 17:18, Sricharan R wrote: From: Robin Murphy In preparation for some upcoming cleverness, rework the control flow in of_iommu_configure() to minimise duplication and improve the propogation of errors. It's also as good a time as any to switch

Re: [PATCH V7 10/11] iommu/arm-smmu: Clean up early-probing workarounds

On 23.01.2017 17:18, Sricharan R wrote: From: Robin Murphy Now that the appropriate ordering is enforced via profe-deferral of masters in core code, rip it all out and bask in the simplicity. Acked-by: Will Deacon Signed-off-by: Robin Murphy

Re: [PATCH V7 01/11] iommu/of: Refactor of_iommu_configure() for error handling

Hi Robin, On 25.01.2017 18:35, Robin Murphy wrote: Hi Tomasz, On 25/01/17 17:17, Tomasz Nowicki wrote: Hi Sricharan, On 23.01.2017 17:18, Sricharan R wrote: From: Robin Murphy <robin.mur...@arm.com> In preparation for some upcoming cleverness, rework the control flow in of_iommu_con

Re: [PATCH v8 12/18] irqdomain: Add irq domain MSI and MSI_REMAP flags

yngier <marc.zyng...@arm.com> Reviewed-by: Tomasz Nowicki <tomasz.nowi...@caviumnetworks.com> Thanks, Tomasz --- v7 -> v8: - remove h variable in irq_domain_hierarchical_is_msi_remap - add Marc's R-b v6: - add IRQ_DOMAIN_FLAG_MSI as suggested by Marc - add irq_domain_is_msi, ir

Re: [PATCH v8 13/18] genirq/msi: Set IRQ_DOMAIN_FLAG_MSI on MSI domain creation

On 11.01.2017 10:41, Eric Auger wrote: Now we have a flag value indicating an IRQ domain implements MSI, let's set it on msi_create_irq_domain(). Signed-off-by: Eric Auger <eric.au...@redhat.com> Reviewed-by: Marc Zyngier <marc.zyng...@arm.com> Reviewed-by: Tomasz Nowicki

Re: [PATCH v8 14/18] irqdomain: irq_domain_check_msi_remap

On 17.01.2017 15:06, Tomasz Nowicki wrote: On 17.01.2017 14:53, Auger Eric wrote: Hi Tomasz, On 17/01/2017 14:40, Tomasz Nowicki wrote: On 11.01.2017 10:41, Eric Auger wrote: This new function checks whether all MSI irq domains implement IRQ remapping. This is useful to understand whether

Re: [PATCH v8 18/18] iommu/arm-smmu: Do not advertise IOMMU_CAP_INTR_REMAP anymore

, let's correct this. Signed-off-by: Eric Auger <eric.au...@redhat.com> Acked-by: Will Deacon <will.dea...@arm.com> For patches [15-18]: Reviewed-by: Tomasz Nowicki <tomasz.nowi...@caviumnetworks.com> Thanks, Tomasz --- v7 -> v8: - added Will's A-b --- drivers/io

Re: [PATCH v3] IOMMU: SMMUv2: Support for Extended Stream ID (16 bit)

1:1 map). Eventually SMMU drops such device because the stream ID is out of range. This is the case for all devices connected as external endpoints on ThunderX. To fix above issue enable the Extended Stream ID optional feature when available. Please add my: Reviewed-by: To

Re: [PATCH v3] IOMMU: SMMUv2: Support for Extended Stream ID (16 bit)

On 19.01.2017 11:57, Aleksey Makarov wrote: Hi Tomasz, On 01/19/2017 11:55 AM, Tomasz Nowicki wrote: Hi Aleksey, On 17.01.2017 16:14, Aleksey Makarov wrote: Enable the Extended Stream ID feature when available. This patch on top of series "KVM PCIe/MSI passthrough on ARM/ARM64 and

[PATCH 1/1] iommu/arm-smmu: Fix for ThunderX erratum #27704

ASIDs consistently for all SMMU instances. Signed-off-by: Tomasz Nowicki <t...@semihalf.com> Reviewed-by: Robin Murphy <robin.mur...@arm.com> Reviewed-by: Tirumalesh Chalamarla <tirumalesh.chalama...@cavium.com> --- drivers/iommu/arm-smmu.c | 3 +++ 1 file changed, 3 i

Re: [PATCH v8 06/18] iommu: iommu_get_group_resv_regions

-by: Eric Auger <eric.au...@redhat.com> Reviewed-by: Tomasz Nowicki <tomasz.nowi...@caviumnetworks.com> Thanks, Tomasz --- v6 -> v7: - avoid merge of regions of different type v3 -> v4: - take the iommu_group lock in iommu_get_group_resv_regions - the list now is sorted and ov

Re: [PATCH v8 02/18] iommu: Rename iommu_dm_regions into iommu_resv_regions

address space or because they are not translated by the IOMMU and need special handling) So let's rename the struct and also the callbacks. Signed-off-by: Eric Auger <eric.au...@redhat.com> Acked-by: Robin Murphy <robin.mur...@arm.com> Reviewed-by: Tomasz Nowicki <tomasz.nowi...@cav

Re: [PATCH v8 01/18] iommu/dma: Allow MSI-only cookies

cating a region of their IOVA space to a managed cookie, and extend the mapping routine to implement a trivial linear allocator in such cases, to avoid the needless overhead of a full-blown IOVA domain. Signed-off-by: Robin Murphy <robin.mur...@arm.com> Reviewed-by: Tomasz Nowicki

Re: [PATCH v8 05/18] iommu: Only map direct mapped regions

On 11.01.2017 10:41, Eric Auger wrote: As we introduced new reserved region types which do not require mapping, let's make sure we only map direct mapped regions. Signed-off-by: Eric Auger <eric.au...@redhat.com> Reviewed-by: Tomasz Nowicki <tomasz.nowi...@caviumnetworks.com> Th

Re: [PATCH v8 04/18] iommu: iommu_alloc_resv_region

On 11.01.2017 10:41, Eric Auger wrote: Introduce a new helper serving the purpose to allocate a reserved region. This will be used in iommu driver implementing reserved region callbacks. Signed-off-by: Eric Auger <eric.au...@redhat.com> Reviewed-by: Tomasz Nowicki <to

Re: [PATCH v8 10/18] iommu/arm-smmu: Implement reserved region get/put callbacks

com> Reviewed-by: Tomasz Nowicki <tomasz.nowi...@caviumnetworks.com> Thanks, Tomasz --- v3 -> v4: - do not handle PCI host bridge windows anymore - encode prot RFC v2 -> v3: - use existing get/put_resv_regions RFC v1 -> v2: - use defines for MSI IOVA base and length --- drivers/

Re: [PATCH v8 11/18] iommu/arm-smmu-v3: Implement reserved region get/put callbacks

sysfs. Signed-off-by: Eric Auger <eric.au...@redhat.com> Acked-by: Will Deacon <will.dea...@arm.com> Reviewed-by: Tomasz Nowicki <tomasz.nowi...@caviumnetworks.com> Thanks, Tomasz --- v7 -> v8: - added Will's A-b v4: creation --- drivers/iommu/arm-smmu-v3.c | 28 ++

Re: [PATCH v8 14/18] irqdomain: irq_domain_check_msi_remap

On 17.01.2017 14:53, Auger Eric wrote: Hi Tomasz, On 17/01/2017 14:40, Tomasz Nowicki wrote: On 11.01.2017 10:41, Eric Auger wrote: This new function checks whether all MSI irq domains implement IRQ remapping. This is useful to understand whether VFIO passthrough is safe with respect

Re: [PATCH v8 14/18] irqdomain: irq_domain_check_msi_remap

On 11.01.2017 10:41, Eric Auger wrote: This new function checks whether all MSI irq domains implement IRQ remapping. This is useful to understand whether VFIO passthrough is safe with respect to interrupts. On ARM typically an MSI controller can sit downstream to the IOMMU without preventing

Re: [PATCH v6 13/16] drivers: iommu: arm-smmu: add IORT configuration

l_interrupt_offset); With this fix, I run VM with several PCI devices (NIC, SATA) in passthrough mode successfully on ACPI host using ThunderX 1-socket board. Also, for my tests I used Eric's patches: https://github.com/eauger/linux/commits/v4.9-rc3-reserved-rfc-v2 Including bug fix above: Te

Re: [PATCH v7 00/16] ACPI IORT ARM SMMU support

/lpieralisi/linux.git acpi/iort-smmu-v7 Tested on Juno and FVP models for ARM SMMU v1 and v3 probing path. For all series: Reviewed-by: Tomasz Nowicki <t...@semihalf.com> Thanks, Tomasz ___ iommu mailing list iommu@lists.linux-foundation.org

Re: [PATCH 1/1] iommu/arm-smmu: Fix for ThunderX erratum #27704

On 11.01.2017 13:19, Robin Murphy wrote: On 11/01/17 11:51, Tomasz Nowicki wrote: The goal of erratum #27704 workaround was to make sure that ASIDs and VMIDs are unique across all SMMU instances on affected Cavium systems. Currently, the workaround code partitions ASIDs and VMIDs by increasing

Re: [PATCH 1/1] iommu/arm-smmu: Fix for ThunderX erratum #27704

On 12.01.2017 07:41, Tomasz Nowicki wrote: On 11.01.2017 13:19, Robin Murphy wrote: On 11/01/17 11:51, Tomasz Nowicki wrote: The goal of erratum #27704 workaround was to make sure that ASIDs and VMIDs are unique across all SMMU instances on affected Cavium systems. Currently, the workaround

Re: [PATCH v8 00/18] KVM PCIe/MSI passthrough on ARM/ARM64 and IOVA reserved regions

with internal 10G VNIC and Intel IXGBE NIC. Please feel free to add my: Tested-by: Tomasz Nowicki <tomasz.nowi...@caviumnetworks.com> Thanks, Tomasz ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/li

[PATCH 1/1] iommu/arm-smmu: Fix for ThunderX erratum #27704

upport for stage-1 AArch64 contexts for Cavium SMMUv2 model so that we use ASIDs consistently. Signed-off-by: Tomasz Nowicki <t...@semihalf.com> --- drivers/iommu/arm-smmu.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index a60cded..ae

Re: [RFC PATCH 29/30] vfio: Add support for Shared Virtual Memory

Hi Jean, On 27.02.2017 20:54, Jean-Philippe Brucker wrote: Add two new ioctl for VFIO devices. VFIO_DEVICE_BIND_TASK creates a bond between a device and a process address space, identified by a device-specific ID named PASID. This allows the device to target DMA transactions at the process

Re: [RFC PATCH 30/30] vfio: Allow to bind foreign task

On 27.02.2017 20:54, Jean-Philippe Brucker wrote: Let the process that owns the device create an address space bond on behalf of another process. We add a pid argument to the BIND_TASK ioctl, allowing the caller to bind a foreign task. The expected program flow in this case is: * Process A

Re: [RFC PATCH 29/30] vfio: Add support for Shared Virtual Memory

On 26.04.2017 12:08, Jean-Philippe Brucker wrote: On 26/04/17 07:53, Tomasz Nowicki wrote: +mutex_lock(>tasks_lock); +list_for_each_entry(vfio_task, >tasks, list) { +if (vfio_task->pasid != svm.pasid) +continue; + +ret = iommu_un

Re: [RFC PATCH 07/30] iommu/arm-smmu-v3: Add second level of context descriptor table

Hi Jean, On 27.02.2017 20:54, Jean-Philippe Brucker wrote: @@ -1213,17 +1356,59 @@ static void arm_smmu_free_cd_tables(struct arm_smmu_master_data *master) __maybe_unused static int arm_smmu_alloc_cd(struct arm_smmu_master_data *master) { + int ssid; + int i, ret; struct

Re: [RFC PATCH 04/30] iommu/arm-smmu-v3: Add support for PCI ATS

Hi Jean, On 27.02.2017 20:54, Jean-Philippe Brucker wrote: +/* + * Returns -ENOSYS if ATS is not supported either by the device or by the SMMU + */ +static int arm_smmu_enable_ats(struct arm_smmu_master_data *master) +{ + int ret; + size_t stu; + struct pci_dev *pdev; +

[PATCH 1/1] iommu/iova: Make rcache flush optional on IOVA allocation failure

pick the slowest option to proceed. This patch reworks flushed_rcache local flag to be additional function argument instead and control rcache flush step. Also, it updates all users to do the flush as the last chance. Signed-off-by: Tomasz Nowicki <tomasz.nowi...@caviumnetworks.com> -

[PATCH 0/1] Optimise IOVA allocations for PCI devices

solution is that machines with relatively small numbers of CPUs may get DAC addresses more frequently for PCI devices. Please let me know your thoughts. Tomasz Nowicki (1): iommu/iova: Make rcache flush optional on IOVA allocation failure drivers/iommu/amd_iommu.c | 5 +++-- drivers/iomm

Re: [PATCH 1/1] iommu/iova: Make rcache flush optional on IOVA allocation failure

Hi Robin, On 18.09.2017 18:02, Robin Murphy wrote: Hi Tomasz, On 18/09/17 11:56, Tomasz Nowicki wrote: Since IOVA allocation failure is not unusual case we need to flush CPUs' rcache in hope we will succeed in next round. However, it is useful to decide whether we need rcache flush step

Re: [PATCH 1/1] iommu/iova: Make rcache flush optional on IOVA allocation failure

Hi Nate, On 19.09.2017 04:57, Nate Watterson wrote: Hi Tomasz, On 9/18/2017 12:02 PM, Robin Murphy wrote: Hi Tomasz, On 18/09/17 11:56, Tomasz Nowicki wrote: Since IOVA allocation failure is not unusual case we need to flush CPUs' rcache in hope we will succeed in next round. However

[PATCH V2 0/1] Optimise IOVA allocations for PCI devices

solution is that machines with relatively small numbers of CPUs may get DAC addresses more frequently for PCI devices. Please let me know your thoughts. Changelog: v1 --> v2 - add missing documentation - fix typo Tomasz Nowicki (1): iommu/iova: Make rcache flush optional on IOVA allocatio

[PATCH V2 1/1] iommu/iova: Make rcache flush optional on IOVA allocation failure

pick the slowest option to proceed. This patch reworks flushed_rcache local flag to be additional function argument instead and control rcache flush step. Also, it updates all users to do the flush as the last chance. Signed-off-by: Tomasz Nowicki <tomasz.nowi...@caviumnetworks.com&

Re: [PATCH v5 3/6] iommu/iova: Extend rbtree node caching

Hi Robin, On 21.09.2017 17:52, Robin Murphy wrote: The cached node mechanism provides a significant performance benefit for allocations using a 32-bit DMA mask, but in the case of non-PCI devices or where the 32-bit space is full, the loss of this benefit can be significant - on large systems

Re: [PATCH v4 5/6] iommu/iova: Extend rbtree node caching

Hi Robin, On 19.09.2017 18:31, Robin Murphy wrote: The cached node mechanism provides a significant performance benefit for allocations using a 32-bit DMA mask, but in the case of non-PCI devices or where the 32-bit space is full, the loss of this benefit can be significant - on large systems

Re: [PATCH V2 0/1] Optimise IOVA allocations for PCI devices

Hi Joerg, Can you please have a look and see if you are fine with this patch? Thanks in advance, Tomasz On 20.09.2017 10:52, Tomasz Nowicki wrote: Here is my test setup where I have stareted performance measurements. PCIe - TX - PCIe

Re: [PATCH V2 0/1] Optimise IOVA allocations for PCI devices

Hi Joerg, Can you please have a look and see if you are fine with this patch? Thanks in advance, Tomasz On 20.09.2017 10:52, Tomasz Nowicki wrote: Here is my test setup where I have stareted performance measurements. PCIe - TX - PCIe

Re: [PATCH V2 0/1] Optimise IOVA allocations for PCI devices

Hi Joerg, On 12.10.2017 12:04, Joerg Roedel wrote: Hi Tomasz, On Thu, Oct 12, 2017 at 11:40:27AM +0200, Tomasz Nowicki wrote: Can you please have a look and see if you are fine with this patch? How do these changes relate to Robin's IOVA optimizations already in the iommu-tree

[PATCH V1 1/1] iommu: Make sure device's ID array elements are unique

multiple times too which for some IOMMU drivers is illegal and causes kernel panic. Rule out ID duplication prior to device ID array registration. CC: sta...@vger.kernel.org # v4.14+ Signed-off-by: Tomasz Nowicki <tomasz.nowi...@caviumnetworks.com> --- drivers/iommu/iommu.

[PATCH V1 0/1] Fix kernel panic caused by device ID duplication presented to the IOMMU

ossible to have two identical SIDs. The question is what we should do about such case. Presented patch prevents from registering the same ID so that SMMUv3 is not complaining later on. Tomasz Nowicki (1): iommu: Make sure device's ID array elements are unique drivers/iom

Re: [PATCH V1 0/1] Fix kernel panic caused by device ID duplication presented to the IOMMU

Hi Robin, On 19.12.2017 17:34, Robin Murphy wrote: Hi Tomasz, On 19/12/17 15:13, Tomasz Nowicki wrote: Here is my lspci output of ThunderX2 for which I am observing kernel panic coming from SMMUv3 driver -> arm_smmu_write_strtab_ent() -> BUG_ON(ste_live): # lspci -vt -[:00]-+-00

Re: [PATCH V1 1/1] iommu: Make sure device's ID array elements are unique

On 19.12.2017 17:37, Alex Williamson wrote: On Tue, 19 Dec 2017 16:20:21 +0100 Tomasz Nowicki <tomasz.nowi...@caviumnetworks.com> wrote: While iterating over DMA aliases for a PCI device, for some rare cases (i.e. PCIe-to-PCI/X bridges) we may get exactly the same ID as initial child

Re: [PATCH 1/4] iommu: Add virtio-iommu driver

Hi Jean, On 14.02.2018 15:53, Jean-Philippe Brucker wrote: The virtio IOMMU is a para-virtualized device, allowing to send IOMMU requests such as map/unmap over virtio-mmio transport without emulating page tables. This implementation handles ATTACH, DETACH, MAP and UNMAP requests. The bulk of

Re: [PATCH V1 0/1] Fix kernel panic caused by device ID duplication presented to the IOMMU

Hi Robin, On 19.12.2017 17:34, Robin Murphy wrote: Hi Tomasz, On 19/12/17 15:13, Tomasz Nowicki wrote: Here is my lspci output of ThunderX2 for which I am observing kernel panic coming from SMMUv3 driver -> arm_smmu_write_strtab_ent() -> BUG_ON(ste_live): # lspci -vt -[:00]-+-00

Re: [PATCH v7 0/7] Add virtio-iommu driver

ons(-) > create mode 100644 Documentation/devicetree/bindings/virtio/iommu.txt > create mode 100644 drivers/iommu/virtio-iommu.c > create mode 100644 include/uapi/linux/virtio_iommu.h > I have tested the whole series and Eric's QEMU patchset [4]

Re: [PATCH v4 0/4] Add system mmu support for Armada-806

On 10/23/20 12:33 PM, Robin Murphy wrote: On 2020-10-23 13:19, Tomasz Nowicki wrote: Hi Denis, Sorry for late response, we had to check few things. Please see comments inline. On 10/6/20 3:16 PM, Denis Odintsov wrote: Hi, Am 15.07.2020 um 09:06 schrieb Tomasz Nowicki : The series

Re: [PATCH v4 0/4] Add system mmu support for Armada-806

Hi Denis, Sorry for late response, we had to check few things. Please see comments inline. On 10/6/20 3:16 PM, Denis Odintsov wrote: Hi, Am 15.07.2020 um 09:06 schrieb Tomasz Nowicki : The series is meant to support SMMU for AP806 and a workaround for accessing ARM SMMU 64bit registers

[PATCH v3 0/4] Add system mmu support for Armada-806

for platform devices like SATA and USB. [1]: https://lkml.org/lkml/2018/10/15/373 [2]: https://lkml.org/lkml/2019/7/11/426 Hanna Hawa (1): iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743 Marcin Wojtas (1): arm64: dts: marvell: add SMMU support Tomasz Nowicki (2

[PATCH v3 2/4] iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743

-by: Gregory CLEMENT Signed-off-by: Tomasz Nowicki --- Documentation/arm64/silicon-errata.rst | 3 ++ drivers/iommu/arm-smmu-impl.c | 52 ++ 2 files changed, 55 insertions(+) diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon

[PATCH v3 3/4] dt-bindings: arm-smmu: add compatible string for Marvell Armada-AP806 SMMU-500

CLEMENT Signed-off-by: Tomasz Nowicki --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index d7ceb4c34423..7beca9c00b12

[PATCH v3 4/4] arm64: dts: marvell: add SMMU support

From: Marcin Wojtas Add IOMMU node for Marvell AP806 based SoCs together with platform and PCI device Stream ID mapping. Signed-off-by: Marcin Wojtas Signed-off-by: Tomasz Nowicki --- arch/arm64/boot/dts/marvell/armada-8040.dtsi | 36 +++ arch/arm64/boot/dts/marvell/armada

[PATCH v3 1/4] iommu/arm-smmu: Add SMMU ID2 register fixup hook

and cleaner to do ID fixup right away. In preparation for adding Marvell errata add an extra ID2 fixup hook. Signed-off-by: Tomasz Nowicki --- drivers/iommu/arm-smmu.c | 3 +++ drivers/iommu/arm-smmu.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm

Re: [PATCH v3 0/4] Add system mmu support for Armada-806

Hi Will, On 14.07.2020 10:19, Will Deacon wrote: Hi Tomasz, On Thu, Jul 02, 2020 at 10:16:29PM +0200, Tomasz Nowicki wrote: There were already two versions of series to support SMMU for AP806, including workaround for accessing ARM SMMU 64bit registers. First [1] by Hanna Hawa and second [2

[PATCH v4 2/4] iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743

-by: Gregory CLEMENT Signed-off-by: Tomasz Nowicki --- Documentation/arm64/silicon-errata.rst | 3 ++ drivers/iommu/arm-smmu-impl.c | 45 ++ 2 files changed, 48 insertions(+) diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon

[PATCH v4 0/4] Add system mmu support for Armada-806

nna Hawa (1): iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743 Marcin Wojtas (1): arm64: dts: marvell: add SMMU support Tomasz Nowicki (2): iommu/arm-smmu: Call configuration impl hook before consuming features dt-bindings: arm-smmu: add compatible string for Marv

[PATCH v4 1/4] iommu/arm-smmu: Call configuration impl hook before consuming features

we start consuming them. Since the Cavium quirk (the only user) does not alter features it is safe to do so. Suggested-by: Robin Murphy Signed-off-by: Tomasz Nowicki --- drivers/iommu/arm-smmu.c | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm

[PATCH v4 4/4] arm64: dts: marvell: add SMMU support

From: Marcin Wojtas Add IOMMU node for Marvell AP806 based SoCs together with platform and PCI device Stream ID mapping. Signed-off-by: Marcin Wojtas Signed-off-by: Tomasz Nowicki --- arch/arm64/boot/dts/marvell/armada-7040.dtsi | 28 + arch/arm64/boot/dts/marvell/armada-8040

[PATCH v4 3/4] dt-bindings: arm-smmu: add compatible string for Marvell Armada-AP806 SMMU-500

Hawa Signed-off-by: Gregory CLEMENT Signed-off-by: Tomasz Nowicki --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index

Re: [PATCH v3 4/4] arm64: dts: marvell: add SMMU support

On 03.07.2020 11:16, Robin Murphy wrote: On 2020-07-02 21:16, Tomasz Nowicki wrote: From: Marcin Wojtas Add IOMMU node for Marvell AP806 based SoCs together with platform and PCI device Stream ID mapping. Signed-off-by: Marcin Wojtas Signed-off-by: Tomasz Nowicki ---   arch/arm64/boot/dts

Re: [PATCH v3 1/4] iommu/arm-smmu: Add SMMU ID2 register fixup hook

On 03.07.2020 10:24, Robin Murphy wrote: On 2020-07-02 21:16, Tomasz Nowicki wrote: We already have 'cfg_probe' hook which meant to override and apply workarounds while probing ID registers. However, 'cfg_probe' is called at the very end and therefore for some cases fixing up things becomes

Re: [PATCH v3 3/4] dt-bindings: arm-smmu: add compatible string for Marvell Armada-AP806 SMMU-500

On 03.07.2020 11:05, Robin Murphy wrote: On 2020-07-02 21:16, Tomasz Nowicki wrote: Add specific compatible string for Marvell usage due to errata of accessing 64bits registers of ARM SMMU, in AP806. AP806 SoC uses the generic ARM-MMU500, and there's no specific implementation of Marvell

Re: [PATCH v3 2/4] iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743

On 03.07.2020 11:03, Robin Murphy wrote: On 2020-07-02 21:16, Tomasz Nowicki wrote: From: Hanna Hawa Due to erratum #582743, the Marvell Armada-AP806 can't access 64bit to ARM SMMUv2 registers. Provide implementation relevant hooks: - split the writeq/readq to two accesses of writel/readl

Re: [PATCH v4 3/4] dt-bindings: arm-smmu: add compatible string for Marvell Armada-AP806 SMMU-500

On 15.07.2020 12:36, Robin Murphy wrote: On 2020-07-15 08:06, Tomasz Nowicki wrote: Add specific compatible string for Marvell usage due to errata of accessing 64bits registers of ARM SMMU, in AP806. AP806 SoC uses the generic ARM-MMU500, and there's no specific implementation of Marvell

Re: [PATCH v4 2/4] iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743

On 15.07.2020 12:32, Robin Murphy wrote: On 2020-07-15 08:06, Tomasz Nowicki wrote: From: Hanna Hawa Due to erratum #582743, the Marvell Armada-AP806 can't access 64bit to ARM SMMUv2 registers. Provide implementation relevant hooks: - split the writeq/readq to two accesses of writel/readl

[PATCH 1/1] arm64: dts: marvell: keep SMMU disabled by default for Armada 7040 and 8040

tion. Fixes: 83a3545d9c37 ("arm64: dts: marvell: add SMMU support") Cc: # 5.9+ Signed-off-by: Tomasz Nowicki --- arch/arm64/boot/dts/marvell/armada-7040.dtsi | 4 arch/arm64/boot/dts/marvell/armada-8040.dtsi | 4 2 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/