Hi Hiroshi,
On Wed, Jan 16, 2013 at 04:43:21PM +, Hiroshi Doyu wrote:
Will Deacon will.dea...@arm.com wrote @ Wed, 16 Jan 2013 12:51:14 +0100:
Given that this information is not discoverable, it needs to be encoded
in the device tree, but where? I can see two approaches:
1
This patch adds a description of the device tree binding for the ARM
System MMU architecture.
Cc: Rob Herring robherri...@gmail.com
Cc: Andreas Herrmann andreas.herrm...@calxeda.com
Signed-off-by: Will Deacon will.dea...@arm.com
---
Hello,
The driver for this is still a WIP. Both Andreas
Hi Rob,
On Fri, Apr 05, 2013 at 05:43:06PM +0100, Rob Herring wrote:
On 04/04/2013 11:50 AM, Will Deacon wrote:
This patch adds a description of the device tree binding for the ARM
System MMU architecture.
Cc: Rob Herring robherri...@gmail.com
Cc: Andreas Herrmann andreas.herrm
On Fri, Apr 05, 2013 at 07:25:26PM +0100, Rob Herring wrote:
On 04/05/2013 11:57 AM, Will Deacon wrote:
Hi Rob,
On Fri, Apr 05, 2013 at 05:43:06PM +0100, Rob Herring wrote:
[...]
+- compatible: Should be one of arm,smmu-v1 or arm,smmu-v2
+ depending
Hi Olav,
On Fri, Apr 05, 2013 at 09:44:49PM +0100, Olav Haugan wrote:
On 4/4/2013 9:50 AM, Will Deacon wrote:
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
new file mode 100644
index 000..938325f
--- /dev
On Mon, Apr 08, 2013 at 06:03:54PM +0100, Olav Haugan wrote:
Hi Will,
Hello,
Generally, the StreamIDs are fixed in hardware (as a function of various AXI
bits -- see the SMMU integration guide) and cannot be set by software.
Furthermore, when the StreamIDs have an implicit effect on IOMMU
This patch adds a description of the device tree binding for the ARM
System MMU architecture.
Cc: Rob Herring robherri...@gmail.com
Cc: Andreas Herrmann andreas.herrm...@calxeda.com
Signed-off-by: Will Deacon will.dea...@arm.com
---
.../devicetree/bindings/iommu/arm,smmu.txt | 66
On Tue, Apr 23, 2013 at 11:54:53PM +0100, Olav Haugan wrote:
Hi Will,
Hello again,
On 4/18/2013 12:01 PM, Will Deacon wrote:
No. The device-tree describes the *hardware*, as per usual. The StreamIDs
are fixed properties of the SoC and we can't change them from Linux, so we
describe all
On Mon, May 13, 2013 at 10:50:20AM +0100, Andreas Herrmann wrote:
Hi Will,
Hi Andreas,
so far, I thought, that this proposal is fine. After I have tried to
make use of the binding I have some points that might need further
disucssion.
Sure, although I've been using the binding without
On Mon, May 13, 2013 at 10:07:24AM +0100, Andreas Herrmann wrote:
On Tue, May 07, 2013 at 04:26:02PM -0400, Olav Haugan wrote:
I think you misunderstood me. I am talking about having for example 1
master with two (2) context banks so that StreamID 1 goes to CB0 and
StreamID 2 goes to CB1.
On Tue, May 21, 2013 at 11:25:01AM +0100, Andreas Herrmann wrote:
On Mon, May 20, 2013 at 06:18:41AM -0400, Will Deacon wrote:
That also looks fine to me, although I'd like to write the parsing code in
my driver before I commit to anything!
Right, I hacked that up this afternoon and it seems
...@codeaurora.org
Cc: Joerg Roedel j...@8bytes.org
Signed-off-by: Will Deacon will.dea...@arm.com
---
drivers/iommu/Kconfig| 13 +
drivers/iommu/Makefile |1 +
drivers/iommu/arm-smmu.c | 1965 ++
3 files changed, 1979 insertions(+)
create mode 100644
...@codeaurora.org
Cc: Joerg Roedel j...@8bytes.org
Signed-off-by: Will Deacon will.dea...@arm.com
---
drivers/iommu/Kconfig| 13 +
drivers/iommu/Makefile |1 +
drivers/iommu/arm-smmu.c | 1969 ++
3 files changed, 1983 insertions(+)
create mode 100644
Apart from fault handling and page table manipulation, we don't care
about memory ordering between SMMU control registers and normal,
cacheable memory, so use the _relaxed I/O accessors wherever possible.
Signed-off-by: Will Deacon will.dea...@arm.com
---
drivers/iommu/arm-smmu.c | 6 +++---
1
probing has completed
(2013-09-17 12:03:11 +0100)
Dan Carpenter (2):
iommu/arm-smmu: fix a signedness bug
iommu/arm-smmu: fix iommu_present() test in init
Will Deacon (1):
iommu/arm-smmu: don't enable SMMU device until
On Tue, Sep 24, 2013 at 04:14:30PM +0100, Andreas Herrmann wrote:
iommu/arm-smmu: Remove bogus semicolon from if conditions
Those prevented proper registration of arm_smmu_ops.
Signed-off-by: Andreas Herrmann andreas.herrm...@calxeda.com
---
drivers/iommu/arm-smmu.c |4 ++--
1 file
On Tue, Sep 24, 2013 at 04:06:54PM +0100, Andreas Herrmann wrote:
Hi,
Hi Andreas,
Following patches fix misc issues, that I've seen when using arm-smmu
driver with MMU-400.
Thanks for the patches! I'll respond to each one in turn.
Will
___
iommu
On Tue, Sep 24, 2013 at 04:06:56PM +0100, Andreas Herrmann wrote:
Currently it is derived from smmu resource size. If the resource size
is wrongly specified (e.g. too large) this leads to a miscalculation
and can cause undefined behaviour when context bank registers are
modified.
On Tue, Sep 24, 2013 at 04:06:58PM +0100, Andreas Herrmann wrote:
With the right (or wrong;-) definition of v1 SMMU node in DTB it is
possible to trigger a division by zero in arm_smmu_init_domain_context
(if number of context irqs is 0):
if (smmu-version == 1) {
On Tue, Sep 24, 2013 at 04:06:57PM +0100, Andreas Herrmann wrote:
... otherwise it is impossible for the low level iommu driver to
figure out which pte flags should be used.
In __map_sg_chunk we can derive the flags from dma_data_direction.
In __iommu_create_mapping we should treat the
On Tue, Sep 24, 2013 at 04:07:01PM +0100, Andreas Herrmann wrote:
Signed-off-by: Andreas Herrmann andreas.herrm...@calxeda.com
---
drivers/iommu/arm-smmu.c |9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index
On Tue, Sep 24, 2013 at 07:32:47PM +0100, Andreas Herrmann wrote:
On Tue, Sep 24, 2013 at 11:42:52AM -0400, Will Deacon wrote:
On Tue, Sep 24, 2013 at 04:07:01PM +0100, Andreas Herrmann wrote:
Signed-off-by: Andreas Herrmann andreas.herrm...@calxeda.com
---
drivers/iommu/arm-smmu.c
On Tue, Sep 24, 2013 at 07:07:20PM +0100, Andreas Herrmann wrote:
On Tue, Sep 24, 2013 at 11:34:57AM -0400, Will Deacon wrote:
On Tue, Sep 24, 2013 at 04:06:56PM +0100, Andreas Herrmann wrote:
Currently it is derived from smmu resource size. If the resource size
is wrongly specified (e.g
should be allowed.
Cc: Marek Szyprowski m.szyprow...@samsung.com
Signed-off-by: Andreas Herrmann andreas.herrm...@calxeda.com
Acked-by: Will Deacon will.dea...@arm.com
This one should go via the dma-mapping tree.
Will
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On Thu, Sep 26, 2013 at 11:36:16PM +0100, Andreas Herrmann wrote:
With the right (or wrong;-) definition of v1 SMMU node in DTB it is
possible to trigger a division by zero in arm_smmu_init_domain_context
(if number of context irqs is 0):
if (smmu-version == 1) {
On Thu, Sep 26, 2013 at 11:36:13PM +0100, Andreas Herrmann wrote:
This should ensure that arm-smmu is initialized before other drivers
start handling devices that propably need smmu support.
Also remove module_exit function as we most likely never want to
unload this driver.
Doesn't hurt to
Hi Andreas,
On Thu, Sep 26, 2013 at 11:36:14PM +0100, Andreas Herrmann wrote:
Currently it is derived from smmu resource size. In case of a
mismatchin between the two calculations trust DT more than register
values and overwrite cb_base.
I thought the driver already favoured the DT?
@@
On Fri, Sep 27, 2013 at 11:39:49AM +0100, Andreas Herrmann wrote:
On Fri, Sep 27, 2013 at 06:23:07AM -0400, Will Deacon wrote:
What do you think?
Yes, that should suffice.
I know it's clear for us but what about a short comment to emphasize
that we expect to find at least one context irq
On Fri, Sep 27, 2013 at 11:23:59AM +0100, Andreas Herrmann wrote:
On Fri, Sep 27, 2013 at 05:51:57AM -0400, Will Deacon wrote:
Hi Andreas,
On Thu, Sep 26, 2013 at 11:36:14PM +0100, Andreas Herrmann wrote:
Currently it is derived from smmu resource size. In case of a
mismatchin
On Fri, Sep 27, 2013 at 12:05:21PM +0100, Andreas Herrmann wrote:
On Fri, Sep 27, 2013 at 06:51:53AM -0400, Will Deacon wrote:
Well, we should already print the device is 0x%lx bytes but only mapped
0x%lx! message, which I think is enough to go and figure out what happened.
No, you can map
Hi Andreas,
On Thu, Sep 26, 2013 at 11:36:19PM +0100, Andreas Herrmann wrote:
(Depending on DT information and module parameters) each device is put
into its own protection domain (if possible). For configuration with
one or just a few masters per SMMU that is easy to achieve.
In case of
On Mon, Sep 30, 2013 at 06:17:16PM +0100, Andreas Herrmann wrote:
On Mon, Sep 30, 2013 at 12:06:15PM -0400, Will Deacon wrote:
On Mon, Sep 30, 2013 at 02:56:21PM +0100, Andreas Herrmann wrote:
After reset these registers have unknown values.
This might cause problems when evaluating
On Tue, Oct 01, 2013 at 01:39:04PM +0100, Andreas Herrmann wrote:
Hi,
here a reworked set of patches. Hopefully all comments addressed.
Cheers Andreas! I've taken the first 5. Whilst I like the cleanup you've
made to the final patch, I'll need an Ack from Rob until I can take anything
On Tue, Oct 01, 2013 at 07:17:09PM +0100, Andreas Herrmann wrote:
On Tue, Oct 01, 2013 at 09:28:51AM -0400, Rob Herring wrote:
On 10/01/2013 07:39 AM, Andreas Herrmann wrote:
In such a case we have to use secure aliases of some non-secure
registers.
This behaviour is controlled via
On Mon, Oct 07, 2013 at 04:42:27PM +0100, Andreas Herrmann wrote:
On Fri, Sep 27, 2013 at 09:00:01AM -0400, Will Deacon wrote:
On Thu, Sep 26, 2013 at 11:36:19PM +0100, Andreas Herrmann wrote:
+ list_for_each_entry(smmu, arm_smmu_devices, list) {
+ if (arm_smmu_disable_isolation
On Tue, Oct 08, 2013 at 11:42:35AM +0100, Sachin Kamat wrote:
devm_request_and_ioremap is deprecated. Use devm_ioremap_resource
instead.
I already have an identical patch from Julia, queued for 3.13.
Thanks,
Will
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On Tue, Oct 08, 2013 at 10:27:20AM +0100, Andreas Herrmann wrote:
Introduce handling of driver options. Options are set based on DT
information when probing an SMMU device. The first option introduced
is arm,smmu-isolate-devices. (It will be used in the bus notifier
block.)
Signed-off-by:
On Tue, Oct 08, 2013 at 10:27:22AM +0100, Andreas Herrmann wrote:
Ie. use a mask based on smr_mask_bits to map all stream IDs of an SMMU
to one context.
This behaviour is controlled per SMMU node with DT property
arm,smmu-mask-stream-ids and is only allowed if just a single master
is
On Tue, Oct 08, 2013 at 05:40:21PM +0100, Andreas Herrmann wrote:
On Tue, Oct 08, 2013 at 05:20:08PM +0200, Andreas Herrmann wrote:
To be more specific: For SATA I'd need to specify 10 StreamIds. This
would
(1) exceed MAX_MASTER_STREAMIDS (currently it's 8)
(Can easily be fixed by
iommu/arm-smmu: Print context fault information
iommu/arm-smmu: Clear global and context bank fault status registers
Julia Lawall (1):
iommu/arm-smmu: replace devm_request_and_ioremap by devm_ioremap_resource
Will Deacon (1):
iommu/arm-smmu: use relaxed accessors where possible
On Wed, Oct 09, 2013 at 11:38:00PM +0100, Andreas Herrmann wrote:
Introduce handling of driver options. Options are set based on DT
information when probing an SMMU device. The first option introduced
is arm,smmu-isolate-devices. (It will be used in the bus notifier
block.)
Signed-off-by:
On Wed, Oct 09, 2013 at 11:38:03PM +0100, Andreas Herrmann wrote:
In such a case we have to use secure aliases of some non-secure
registers.
This handling is switched on by DT property
arm,smmu-secure-config-access for an SMMU node.
Signed-off-by: Andreas Herrmann
On Wed, Oct 09, 2013 at 11:38:01PM +0100, Andreas Herrmann wrote:
drivers/iommu/arm-smmu.c | 53
++
1 file changed, 53 insertions(+)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 478c8ad..87239e8 100644
---
On Fri, Oct 11, 2013 at 02:24:47PM +0100, Antonios Motakis wrote:
The return value of arm_smmu_iova_to_phys is directly passed to the
user of the IOMMU API via iommu_iova_to_phys; however the ARM SMMU
driver returns -EINVAL on error, which is not consistent with the
rest of the drivers
On Mon, Oct 14, 2013 at 04:17:51PM +0100, Antonios Motakis wrote:
On Mon, Oct 14, 2013 at 2:48 PM, Will Deacon will.dea...@arm.com wrote:
On Fri, Oct 11, 2013 at 02:24:47PM +0100, Antonios Motakis wrote:
The return value of arm_smmu_iova_to_phys is directly passed to the
user of the IOMMU
On Mon, Oct 28, 2013 at 04:44:22PM +, Alex Williamson wrote:
On Fri, 2013-10-18 at 17:08 +0200, Antonios Motakis wrote:
IOMMU groups are expected by certain users of the IOMMU API,
e.g. VFIO. Add new devices found by the SMMU driver to an IOMMU
group to satisfy those users.
Changes
On Fri, Oct 18, 2013 at 09:13:11PM +0100, Andreas Herrmann wrote:
At the moment just handle BUS_NOTIFY_BIND_DRIVER to conditionally
isolate all master devices for an SMMU.
Depending on DT information each device is put into its own protection
domain (if possible). For configuration with one
On Fri, Oct 18, 2013 at 09:13:12PM +0100, Andreas Herrmann wrote:
In such a case we have to use secure aliases of some non-secure
registers.
This handling is switched on by DT property
arm,smmu-secure-config-access for an SMMU node.
This looks fine, but won't apply without the device
On Wed, Oct 09, 2013 at 06:02:38PM +0100, Will Deacon wrote:
Hi Joerg,
Please pull these ARM SMMU updates for 3.13. The bulk of the changes are
from Andreas, who has been having fun running the driver on real hardware. I
expect some additional patches from him in the future to add support
On Fri, Oct 18, 2013 at 09:13:14PM +0100, Andreas Herrmann wrote:
Signed-off-by: Andreas Herrmann andreas.herrm...@calxeda.com
---
arch/arm/boot/dts/ecx-2000.dts| 44
+++--
arch/arm/boot/dts/ecx-common.dtsi |9 +---
drivers/iommu/arm-smmu.c
On Thu, Oct 31, 2013 at 05:31:33PM +, Mark Rutland wrote:
On Wed, Oct 30, 2013 at 10:33:32PM +, Stephen Warren wrote:
I'm afraid I still don't quite understand what a swgroup is.
IIUC, the HW works like this based on comments in a previous patch:
Each bus-master attached to
On Thu, Oct 31, 2013 at 05:40:29PM +, Mark Rutland wrote:
For the ARM SMMU binding, each device has a #stream-id-cells property
describing how many IDs it has, and then the SMMU node has a phandle+args
linkage to each of the devices attached to it, describing their stream IDs.
While this
On Thu, Oct 31, 2013 at 07:25:25PM +, Stephen Warren wrote:
On 10/31/2013 01:16 PM, Stephen Warren wrote:
Hmm. That's interesting. I see that the ARM SMMU has a list of the
clients it affects, whereas this Tegra series puts information into each
client device about the SMMU(s) that
On Fri, Nov 01, 2013 at 04:08:52PM +, Stephen Warren wrote:
On 10/31/2013 01:39 PM, Will Deacon wrote:
On Thu, Oct 31, 2013 at 07:25:25PM +, Stephen Warren wrote:
On 10/31/2013 01:16 PM, Stephen Warren wrote:
Hmm. That's interesting. I see that the ARM SMMU has a list
On Mon, Oct 14, 2013 at 06:09:48PM +0100, Will Deacon wrote:
On Mon, Oct 14, 2013 at 04:17:51PM +0100, Antonios Motakis wrote:
On Mon, Oct 14, 2013 at 2:48 PM, Will Deacon will.dea...@arm.com wrote:
On Fri, Oct 11, 2013 at 02:24:47PM +0100, Antonios Motakis wrote:
VFIO will exercise
On Mon, Nov 11, 2013 at 08:31:53AM +, Hiroshi Doyu wrote:
An IOMMU device on the bus is poplulated first, IOMMU'able devices
are done later.
With CONFIG_OF_IOMMU, #stream-id-cells DT binding would be used to
identify whether a device is IOMMU'able or not. If a device is
IOMMU'able,
On Wed, Nov 13, 2013 at 04:06:10PM +, Hiroshi Doyu wrote:
Will Deacon will.dea...@arm.com wrote @ Wed, 13 Nov 2013 15:38:04 +0100:
On Tue, Nov 12, 2013 at 11:34:20PM +, Stephen Warren wrote:
SMMU:
smmu: smmu@xx {
#smmu-cells = 1;
}
Affected
On Wed, Nov 13, 2013 at 05:53:36PM +, Stephen Warren wrote:
On 11/13/2013 10:31 AM, Will Deacon wrote:
On Wed, Nov 13, 2013 at 04:06:10PM +, Hiroshi Doyu wrote:
This can be solved with introducing the fixed size of bitmap. The size
of bitmap can be fixed even per SoC. In tegra we
On Fri, Nov 15, 2013 at 09:42:30AM +, Wei Yongjun wrote:
From: Wei Yongjun yongjun_...@trendmicro.com.cn
Fix to return -ENODEV instead of 0 when context interrupt number
does no match in arm_smmu_device_dt_probe().
Signed-off-by: Wei Yongjun yongjun_...@trendmicro.com.cn
---
On Fri, Nov 15, 2013 at 09:45:03AM +, Wei Yongjun wrote:
From: Wei Yongjun yongjun_...@trendmicro.com.cn
The dereference should be moved below the NULL test.
Signed-off-by: Wei Yongjun yongjun_...@trendmicro.com.cn
---
drivers/iommu/arm-smmu.c | 3 +--
1 file changed, 1
right now.
It seems a little fragile to me too. I'd rather the IOMMU requirement be
described more explicitly.
I think that Will Deacon can do better than I.
I already commented briefly here:
http://www.spinics.net/lists/devicetree/msg11513.html
basically deferring to DT people
On Tue, Nov 19, 2013 at 08:45:02PM +, Rob Herring wrote:
On 11/19/2013 11:35 AM, Will Deacon wrote:
Adding Andreas and Rob for input on potential binding additions to the SMMU.
The above proposal would be an incompatible change. However, I think we
could still deal with a change
On Wed, Nov 20, 2013 at 08:02:10PM +, Rob Herring wrote:
On Wed, Nov 20, 2013 at 12:39 AM, Hiroshi Doyu hd...@nvidia.com wrote:
smmu_a: iommu@ {
#iommu-cells = 2;
};
smmu_b: iommu@ {
#iommu-cells = 3;
};
On Fri, Nov 22, 2013 at 05:35:58PM +, Stephen Warren wrote:
On 11/22/2013 12:41 AM, Grant Likely wrote:
It seems more that IOMMU attachment is closer to being a property of the
bus rather than a property of the device itself. In that context it
would make more sense for the bus device
Hi Stephen,
On Thu, Nov 21, 2013 at 06:40:28PM +, Stephen Warren wrote:
On 11/21/2013 04:00 AM, Will Deacon wrote:
On Wed, Nov 20, 2013 at 08:02:10PM +, Rob Herring wrote:
For the topology above where you are chaining iommu's, I think
something like this is more accurately
is then reworked so that it only reads the page
tables, and can run in a lockless fashion, leaving the mutex to guard
against concurrent mapping threads.
Signed-off-by: Will Deacon will.dea...@arm.com
---
drivers/iommu/arm-smmu.c | 62
1 file changed, 26
-by: Will Deacon will.dea...@arm.com
---
drivers/iommu/arm-smmu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 6dbcaa4433cd..ef77e3dd6dd2 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -1423,9 +1423,8
()
Will Deacon (2):
iommu/arm-smmu: use mutex instead of spinlock for locking page tables
iommu/arm-smmu: remove potential NULL dereference on mapping path
drivers/iommu/arm-smmu.c | 66
1 file changed, 28 insertions(+), 38 deletions(-)
--
1.8.2.2
Previously, all of our mappings were marked as executable, which isn't
usually required. Now that we have the IOMMU_EXEC flag, use that to
determine whether or not a mapping should be marked as executable.
Signed-off-by: Will Deacon will.dea...@arm.com
---
drivers/iommu/arm-smmu.c | 9
With the introduction of the VA_BITS definition for arm64, make use of
it in the driver, allowing up to 42-bits of VA space when configured
with 64k pages.
Signed-off-by: Will Deacon will.dea...@arm.com
---
drivers/iommu/arm-smmu.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff
Whilst most IOMMU mappings should probably be non-executable, there
may be cases (HSA?) where executable mappings are required.
This patch introduces a new mapping flag, IOMMU_EXEC, to indicate that
the mapping should be mapped as executable.
Signed-off-by: Will Deacon will.dea...@arm.com
a.mota...@virtualopensystems.com
Signed-off-by: Will Deacon will.dea...@arm.com
---
drivers/iommu/arm-smmu.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index e46a88700b68..879da20617fb 100644
Hi Hiroshi,
On Wed, Dec 04, 2013 at 07:40:27AM +, Hiroshi Doyu wrote:
On Mon, 25 Nov 2013 14:49:37 +0100
Hiroshi Doyu hd...@nvidia.com wrote:
Hi Joerg,
Do you have some time to review this patch along with the following ones?
[PATCHv6 02/13] iommu/of: introduce a global
)
Wei Yongjun (1):
iommu/arm-smmu: fix error return code in arm_smmu_device_dt_probe()
Will Deacon (2):
iommu/arm-smmu: use mutex instead of spinlock for locking page tables
iommu/arm-smmu: remove potential NULL dereference on mapping path
drivers/iommu/arm-smmu.c
On Tue, Jan 14, 2014 at 09:02:49AM +, Yifan Zhang wrote:
It seems this patch is still not merged yet, any concerns about it ?
No, I was planning to send it at -rc1 with a CC stable.
Will
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Hi Varun, Andreas,
On Tue, Jan 21, 2014 at 05:48:02PM +, Varun Sethi wrote:
+static int arm_smmu_group_notifier(struct notifier_block *nb,
+ unsigned long action, void *data)
+{
+ struct device *dev = data;
+ struct dma_iommu_mapping *mapping;
+
On Wed, Jan 22, 2014 at 01:14:13PM +, Varun Sethi wrote:
On Tue, Jan 21, 2014 at 05:48:02PM +, Varun Sethi wrote:
+static int arm_smmu_group_notifier(struct notifier_block *nb,
+ unsigned long action, void *data) {
+ struct device *dev =
Hi Andreas,
This patch always requires some extra brain cycles when reviewing!
On Thu, Jan 16, 2014 at 12:44:16PM +, Andreas Herrmann wrote:
Try to determine a mask that can be used for all StreamIDs of a master
device. This allows to use just one SMR group instead of
number-of-streamids
On Thu, Jan 16, 2014 at 12:44:17PM +, Andreas Herrmann wrote:
Cc: Andreas Herrmann herrmann.der.u...@googlemail.com
Signed-off-by: Andreas Herrmann andreas.herrm...@calxeda.com
---
drivers/iommu/arm-smmu.c | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
On Thu, Jan 16, 2014 at 12:44:22PM +, Andreas Herrmann wrote:
The new parameters are
dma_addr_t grow_size
Specifies the size by which the mapping will be extended in
case that no sufficient space is left in the mapping to
handle an iova allocation request.
On Wed, Jan 29, 2014 at 05:26:35PM +, Suravee Suthikulanit wrote:
On 1/29/2014 11:16 AM, Andreas Herrmann wrote:
On Wed, Jan 29, 2014 at 11:59:12AM -0500, Suravee Suthikulanit wrote:
Actually, we are using 32 on the AMD system. So, do you think we can set
this to 32 instead?
I think
On Fri, Jan 31, 2014 at 04:24:09PM +, Rob Herring wrote:
On Thu, Jan 30, 2014 at 11:45 AM, Andreas Herrmann
andreas.herrm...@calxeda.com wrote:
Do you agree on increasing MAX_PHANDLE_ARGS to 32?
Yes, but more than that will require a closer look. Please get this
into next early in the
On Thu, Feb 06, 2014 at 05:05:45AM +, Ritesh Harjani wrote:
Hi everyone,
I tried looking for IOMMU support in ARM64 but what I was able to see is
only swiotlb is currently supported.
Based on my understanding for IOMMU support, we need DMA-MAPPING API to
have IOMMU ops field, similar
-by: Yifan Zhang zhan...@marvell.com
Signed-off-by: Will Deacon will.dea...@arm.com
---
drivers/iommu/arm-smmu.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 8911850c9444..9f210de6537e 100644
instead of GFP_KERNEL.
Cc: sta...@vger.kernel.org
Reported-by: Andreas Herrmann andreas.herrm...@calxeda.com
Signed-off-by: Will Deacon will.dea...@arm.com
---
drivers/iommu/arm-smmu.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b
If !CONFIG_ARM_AMBA, we shouldn't try to register ourselves with the
amba_bustype.
Signed-off-by: Will Deacon will.dea...@arm.com
---
drivers/iommu/arm-smmu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 0ae4dd39197f
during
initial table allocation, and moves the dsb required by coherent table
walkers into the helper.
Signed-off-by: Will Deacon will.dea...@arm.com
---
drivers/iommu/arm-smmu.c | 51 +---
1 file changed, 27 insertions(+), 24 deletions(-)
diff --git
actually need to program
CBARn.BPSHCFG for s1-s2-bypass contexts to act as non-shareable in order
for the shareability configured in the corresponding TTBCR not to be
overridden with an outer-shareable attribute.
Signed-off-by: Will Deacon will.dea...@arm.com
---
drivers/iommu/arm-smmu.c | 16
, and noticed a shareability
mismatch between the CPU and the SMMU
These issues are all fixed here and have been tests on both arm and
arm64 based systems.
All feedback welcome,
Will
Will Deacon (4):
iommu/arm-smmu: really fix page table locking
iommu/arm-smmu: fix table flushing during initial
On Thu, Feb 13, 2014 at 04:55:25PM +, Timur Tabi wrote:
On Thu, Feb 6, 2014 at 12:09 PM, Will Deacon will.dea...@arm.com wrote:
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 0ae4dd39197f..6fe7922ecc1d 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu
Hi Joerg,
On Tue, Feb 18, 2014 at 05:50:27PM +, Joerg Roedel wrote:
On Mon, Feb 10, 2014 at 06:32:32PM +, Will Deacon wrote:
- Andreas Herrmann took the driver for a run with a real SATA
controller, which caused the new mutex-based locking to explode
since we require
On Tue, Feb 18, 2014 at 06:36:26PM +, Will Deacon wrote:
On Tue, Feb 18, 2014 at 05:50:27PM +, Joerg Roedel wrote:
I just did quick review of the changes. Was the SATA controller using
the IOMMU through the DMA-API? In this case you would need the IRQ-safe
spinlocks to avoid dead
Hi Joerg,
On Thu, Feb 20, 2014 at 11:29:19AM +, Joerg Roedel wrote:
On Tue, Feb 18, 2014 at 07:21:37PM +, Will Deacon wrote:
FWIW, here's a diff you could apply as a fixup (or I can send a new pull
request if you prefer). It's slightly messy because I had to rename a
parameter
`flags') and pte protection bits (now `prot').
Signed-off-by: Will Deacon will.dea...@arm.com
---
drivers/iommu/arm-smmu.c | 38 +++---
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index
From: Andreas Herrmann andreas.herrm...@calxeda.com
The DT parsing code that determines stream IDs uses
of_parse_phandle_with_args and thus MAX_MASTER_STREAMIDS
is always bound by MAX_PHANDLE_ARGS.
Signed-off-by: Andreas Herrmann andreas.herrm...@calxeda.com
Signed-off-by: Will Deacon will.dea
[will: merged with driver option handling patch]
Signed-off-by: Will Deacon will.dea...@arm.com
---
drivers/iommu/arm-smmu.c | 58 +++-
1 file changed, 48 insertions(+), 10 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index
Will Deacon (2):
iommu/arm-smmu: clean up use of `flags' in page table handling code
iommu/arm-smmu: provide option to dsb macro when publishing tables
.../devicetree/bindings/iommu/arm,smmu.txt | 6 ++
drivers/iommu/arm-smmu.c | 100 ++---
2
On Thu, Feb 27, 2014 at 05:15:38AM +, Ritesh Harjani wrote:
Hi Everyone,
Hi Ritesh,
I was going through some iommu code in arch/arm and of some other
archs code. I have some doubts on this for refactoring and may need
some suggestions from you guys.
1. So, looking at other arch code,
MAX_MASTER_STREAMIDS to MAX_PHANDLE_ARGS
iommu/arm-smmu: support buggy implementations with secure cfg accesses
documentation/iommu: update description of ARM System MMU binding
Will Deacon (3):
iommu/arm-smmu: clean up use of `flags' in page table handling code
iommu/arm-smmu
On Fri, Feb 28, 2014 at 04:17:43PM +, Timur Tabi wrote:
On Fri, Feb 21, 2014 at 11:16 AM, Will Deacon will.dea...@arm.com wrote:
+- calxeda,smmu-secure-config-access : Enable proper handling of buggy
+ implementations that always use secure access
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