On Mon, 2020-09-07 at 12:16 +0200, Fabien Parent wrote:
> Add support for the IOMMU on MT8167
>
> Signed-off-by: Fabien Parent
Reviewed-by: Yong Wu
> ---
>
> V4;
> * Removed HAS_4GB_MODE flag since this SoC does not seem to support it
> V3:
> * use LEG
On Fri, 2020-10-02 at 13:07 +0200, Krzysztof Kozlowski wrote:
> On Wed, Sep 30, 2020 at 03:06:24PM +0800, Yong Wu wrote:
> > Convert MediaTek IOMMU to DT schema.
> >
> > Signed-off-by: Yong Wu
> > ---
> > .../bindings/iommu/mediatek,iommu.txt | 103 ---
Hi Krzysztof,
On Fri, 2020-10-02 at 13:10 +0200, Krzysztof Kozlowski wrote:
> On Wed, Sep 30, 2020 at 03:06:29PM +0800, Yong Wu wrote:
> > This patch adds decriptions for mt8192 IOMMU and SMI.
> >
> > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor transla
On Fri, 2020-10-02 at 13:08 +0200, Krzysztof Kozlowski wrote:
> On Wed, Sep 30, 2020 at 03:06:25PM +0800, Yong Wu wrote:
> > Convert MediaTek SMI to DT schema.
> >
> > Signed-off-by: Yong Wu
> > ---
> > .../mediatek,smi-common.txt | 4
On Mon, 2020-10-12 at 09:18 +0200, Krzysztof Kozlowski wrote:
> On Sat, Oct 10, 2020 at 02:18:11PM +0800, Yong Wu wrote:
> > On Tue, 2020-10-06 at 09:15 +0200, Krzysztof Kozlowski wrote:
> > > On Tue, 6 Oct 2020 at 06:27, Yong Wu wrote:
> > > >
> > > > On
On Mon, 2020-10-12 at 15:26 +0200, Krzysztof Kozlowski wrote:
> On Mon, 12 Oct 2020 at 14:02, Yong Wu wrote:
> >
> > On Mon, 2020-10-12 at 09:18 +0200, Krzysztof Kozlowski wrote:
> > > On Sat, Oct 10, 2020 at 02:18:11PM +0800, Yong Wu wrote:
> > > > On Tue,
On Mon, 2020-10-12 at 19:08 +0200, Krzysztof Kozlowski wrote:
> On Tue, 6 Oct 2020 at 06:27, Yong Wu wrote:
> >
> > On Fri, 2020-10-02 at 13:07 +0200, Krzysztof Kozlowski wrote:
> > > On Wed, Sep 30, 2020 at 03:06:24PM +0800, Yong Wu wrote:
> > > >
On Tue, 2020-10-06 at 09:15 +0200, Krzysztof Kozlowski wrote:
> On Tue, 6 Oct 2020 at 06:27, Yong Wu wrote:
> >
> > On Fri, 2020-10-02 at 13:08 +0200, Krzysztof Kozlowski wrote:
> > > On Wed, Sep 30, 2020 at 03:06:25PM +0800, Yong Wu wrote:
> > > &g
>of_node->fwnode);
ret = iommu_device_register(>iommu);
if (ret)
Then,
Tested-by: Yong Wu
>
> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> index 122925dbe547..6253e98d810c 100644
> --- a/drivers/iommu/mtk_iommu.h
> +++ b/drivers/io
.org/lkml/20200715205120.GA778876@bogus/
>
> Cc: Mike Rapoport
> Cc: David Hildenbrand
> Cc: Yong Wu
> Cc: Yingjoe Chen
> Cc: Christoph Hellwig
> Cc: Rob Herring
> Cc: Matthias Brugger
> Signed-off-by: Miles Chen
>
> ---
>
> Change since v3
> - use
Pi-Hsun and Nicolas. like use
generic_iommu_put_resv_regions.
c) Reword some comment, like add how to use domain-id.
v1:
https://lore.kernel.org/linux-iommu/20200711064846.16007-1-yong...@mediatek.com/
Yong Wu (24):
dt-bindings: iommu: mediatek: Convert IOMMU to DT schema
dt-bindings: memory: medi
Convert MediaTek IOMMU to DT schema.
Signed-off-by: Yong Wu
---
.../bindings/iommu/mediatek,iommu.txt | 103
.../bindings/iommu/mediatek,iommu.yaml| 154 ++
2 files changed, 154 insertions(+), 103 deletions(-)
delete mode 100644 Documentation
Convert MediaTek SMI to DT schema.
Signed-off-by: Yong Wu
---
.../mediatek,smi-common.txt | 49 -
.../mediatek,smi-common.yaml | 100 ++
.../memory-controllers/mediatek,smi-larb.txt | 49 -
.../memory-controllers/mediatek,smi
4 CCU10x4400_ ~ 0x47ff_ larb14: port 4/5
The iova range for CCU0/1(camera control unit) is HW requirement.
Signed-off-by: Yong Wu
Reviewed-by: Rob Herring
---
.../bindings/iommu/mediatek,iommu.yaml| 9 +-
.../mediatek,smi-common.yaml | 5
a preparing patch for supporting
multi-domain.
Signed-off-by: Anan sun
Signed-off-by: Chao Hao
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 28
drivers/iommu/mtk_iommu.h | 5 +
2 files changed, 33 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b
r each iommu-domain can't cross 4G.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 12 +---
drivers/memory/mtk-smi.c | 7 +++
include/soc/mediatek/smi.h | 1 +
3 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
.
And, m4u doesn't have its special pm runtime domain in previous SoC, in
this case dev->power.runtime_status is RPM_SUSPENDED defaultly, thus add
a "dev->pm_domain" checking for the SoC that has pm runtime domain.
Signed-off-by: Yong Wu
---
drivers/iommu/
If the iova is 34bit, the iova[32][33] is the bit0/1 in the tlb flush
register. Add a new macro for this.
there is a minor change unrelated with this patch. it also use the new
macro.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 11 +++
1 file changed, 7 insertions(+), 4
If the iova is over 32bit, the fault status register bit is a little
different. Add a flag for the special register bits.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b
be put in the master's
node.
b) Update the dma_mask:
dma_set_mask_and_coherent(dev, DMA_BIT_MASK(33));
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 47 +++
drivers/iommu/mtk_iommu.h | 3 ++-
2 files changed, 40 insertions(+), 10 deletions(-)
diff --git a/d
is 0xfff0 +
0x10 = 0x1 . but the register only is 32bit. thus HW will get
the end address is 0. To avoid this issue, I add 1M gap for this.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 22 ++
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 23 insertions
Add "struct mtk_iommu_data *" in the "struct mtk_iommu_domain",
reduce the call mtk_iommu_get_m4u_data().
No functional change.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drive
Add mt8192 smi support.
Signed-off-by: Yong Wu
---
drivers/memory/mtk-smi.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index e94c99ca2883..0ec3eff4d92d 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory
Defaultly the iova range is 0-4G. here we add a single-domain(0-4G)
for the previous SoC. this also is a preparing patch for supporting
multi-domains.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c
flush while
m4u power off is unnecessary, just skip it.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 27 ++-
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 052eb72acf69..1e6e6d3fa7f1 100644
MediaTek extend the bit5 in lvl1 and lvl2 descriptor as PA34.
Signed-off-by: Yong Wu
---
drivers/iommu/io-pgtable-arm-v7s.c | 9 +++--
drivers/iommu/mtk_iommu.c | 2 +-
include/linux/io-pgtable.h | 4 ++--
3 files changed, 10 insertions(+), 5 deletions(-)
diff --git
Add "cfg" as a parameter for some macros. This is a preparing patch for
mediatek extend the lvl1 pgtable. No functional change.
Signed-off-by: Yong Wu
---
drivers/iommu/io-pgtable-arm-v7s.c | 34 +++---
1 file changed, 17 insertions(+), 17 deletions(-)
The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
(4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
34bit.
Signed-off-by: Yong Wu
---
drivers/iommu/io-pgtable-arm-v7s.c | 13 ++---
drivers/iommu/mtk_iommu.c | 2 +-
2 files changed, 11
Use the common larb-port header in the source code.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 7 ---
drivers/iommu/mtk_iommu.h | 1 +
drivers/memory/mtk-smi.c | 1 +
include/soc/mediatek/smi.h | 2 --
4 files changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers
-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 24 +++-
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 940b7a9191b2..5625458b21ba 100644
--- a/drivers/iommu/mtk_iommu.c
Use the ias for the valid iova checking in arm_v7s_unmap. This is a
preparing patch for supporting iova 34bit for MediaTek.
BTW, change the ias/oas checking format in arm_v7s_map.
Signed-off-by: Yong Wu
---
drivers/iommu/io-pgtable-arm-v7s.c | 5 ++---
1 file changed, 2 insertions(+), 3
In attach device, it will update the pagetable base address register.
Move the hw_init function also here. Then it only need call
pm_runtime_get/put one time here if m4u has power domain.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 10 ++
1 file changed, 6 insertions(+), 4
, If we preassign CCU port in domain1, then iommu driver
will prepare a independent iommu domain of the special iova range for it,
then the iova got from dma_alloc_attrs(ccu-dev) will locate in its special
range.
This is a preparing patch for multi-domain support.
Signed-off-by: Yong Wu
---
include/dt
Extend the max larb number definition as mt8192 has larb_nr over 16.
Signed-off-by: Yong Wu
Acked-by: Rob Herring
---
.../bindings/memory-controllers/mediatek,smi-larb.yaml| 2 +-
include/dt-bindings/memory/mtk-smi-larb-port.h| 4 ++--
2 files changed, 3 insertions
Put all the macros about smi larb/port togethers, this is a preparing
patch for extending LARB_NR and adding new dom-id support.
Signed-off-by: Yong Wu
Acked-by: Rob Herring
---
include/dt-bindings/memory/mt2712-larb-port.h | 2 +-
include/dt-bindings/memory/mt6779-larb-port.h | 2
On Sat, 2020-05-09 at 16:36 +0800, Chao Hao wrote:
> 1. Start from mt6779, INVLDT_SEL move to offset=0x2c, so we add
>REG_MMU_INV_SEL_GEN2 definition and mt6779 uses it.
> 2. Change PROTECT_PA_ALIGN from 128 byte to 256 byte.
> 3. For REG_MMU_CTRL_REG register, we only need to change bit[2:0],
On Sat, 2020-05-09 at 16:36 +0800, Chao Hao wrote:
> In order to improve performance, we always disable STANDARD_AXI_MODE in
> MISC_CTRL.
>
> Signed-off-by: Chao Hao
> ---
> drivers/iommu/mtk_iommu.c | 8 +++-
> drivers/iommu/mtk_iommu.h | 1 +
> 2 files changed, 8 insertions(+), 1
ite ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
> @@ -785,7 +791,7 @@ static const struct mtk_iommu_plat_data mt2712_data = {
> .has_bclk = true,
> .has_vld_pa_rng = true,
> .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
> - .larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7,
On Sat, 2020-05-09 at 16:36 +0800, Chao Hao wrote:
> For mt6779, MMU_INVLDT_SEL register's offset is changed from
At this patch, the register is still called by "MMU_INV_SEL".
> 0x38 to 0x2c, so we can put inv_sel_reg in the plat_data to
> use it.
> In addition, we renamed it to
n. So rename REG_MMU_MISC_CTRL may be more proper.
>
> This patch only rename the register name, no functional change.
>
> Signed-off-by: Chao Hao
Reviewed-by: Yong Wu
> ---
> drivers/iommu/mtk_iommu.c | 14 +++---
> drivers/iommu/mtk_iommu.h | 2 +-
> 2 files c
After adding device_link between the IOMMU consumer and smi,
the mediatek,larb is unnecessary now.
CC: Matthias Brugger
Signed-off-by: Yong Wu
Reviewed-by: Evan Green
---
arch/arm/boot/dts/mt2701.dtsi | 1 -
arch/arm/boot/dts/mt7623.dtsi | 1 -
2 files changed, 2 deletions(-)
diff --git
After adding device_link between the IOMMU consumer and smi,
the mediatek,larb is unnecessary now.
CC: Matthias Brugger
Signed-off-by: Yong Wu
Reviewed-by: Evan Green
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 16
1 file changed, 16 deletions(-)
diff --git a/arch/arm64
From: Irui Wang
There are two separate hardware encoder blocks inside MT8173. Split
the current mtk-vcodec-enc node to match the hardware architecture.
Signed-off-by: Irui Wang
Signed-off-by: Hsin-Yi Wang
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 60 +---
1
smi-larb driver should run after smi-common, Use device_is_bound to confirm
whether smicommon driver is ready.
CC: Matthias Brugger
Signed-off-by: Yong Wu
---
drivers/memory/mtk-smi.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/mtk-smi.c b/drivers
MediaTek IOMMU has already added the device_link between the consumer
and smi-larb device. If the mdp device call the pm_runtime_get_sync,
the smi-larb's pm_runtime_get_sync also be called automatically.
CC: Minghsiu Tsai
CC: Houlong Wei
Signed-off-by: Yong Wu
Reviewed-by: Evan Green
MediaTek IOMMU has already added the device_link between the consumer
and smi-larb device. If the vcodec device call the pm_runtime_get_sync,
the smi-larb's pm_runtime_get_sync also be called automatically.
CC: Tiffany Lin
Signed-off-by: Yong Wu
Reviewed-by: Evan Green
---
.../media/platform
leaning up "mediatek,larb".
CC: CK Hu
Signed-off-by: Yongqiang Niu
Signed-off-by: Yong Wu
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 9 -
drivers/gpu/drm/mediatek/mtk_disp_rdma.c| 9 -
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 12 +++-
driv
-by: Yong Wu
---
for iommu v1: honghui's mail address is not valid now. I will be
responsible for that file too, So I add myself in it.
---
drivers/iommu/mtk_iommu.c| 18 ++
drivers/iommu/mtk_iommu_v1.c | 12 +++-
2 files changed, 13 insertions(+), 17 deletions(-)
diff
MediaTek IOMMU has already added the device_link between the consumer
and smi-larb device. If the drm device call the pm_runtime_get_sync,
the smi-larb's pm_runtime_get_sync also be called automatically.
CC: CK Hu
CC: Philipp Zabel
Signed-off-by: Yong Wu
Reviewed-by: Evan Green
---
drivers
iommu/2019-January/032387.html
Irui Wang (1):
arm64: dts: mt8173: Separate mtk-vcodec-enc node
Maoguang Meng (2):
media: dt-binding: mtk-vcodec: Separating mtk-vcodec encode node.
media: mtk-vcodec: separate mtk-vcodec-enc node.
Yong Wu (13):
dt-binding: mediatek: Get rid of med
MediaTek IOMMU has already added device_link between the consumer
and smi-larb device. If the jpg device call the pm_runtime_get_sync,
the smi-larb's pm_runtime_get_sync also be called automatically.
CC: Rick Chang
Signed-off-by: Yong Wu
Reviewed-by: Evan Green
---
drivers/media/platform/mtk
, Add DL_FLAG_STATELESS to avoid the smi-common clocks be gated when
probe.
CC: Matthias Brugger
Suggested-by: Tomasz Figa
Signed-off-by: Yong Wu
---
drivers/memory/mtk-smi.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/memory/mtk-smi.c b
From: Maoguang Meng
MTK H264 Encoder(VENC_SYS) and VP8 Encoder(VENC_LT_SYS) are two
independent hardware instance. They have their owner interrupt,
register mapping, and special clocks.
This patch seperates the two instance. This is a preparing patch for
adding device_link between the larbs and
After adding device_link between the iommu consumer and smi-larb,
the pm_runtime_get(_sync) of smi-larb and smi-common will be called
automatically. we can get rid of mtk_smi_larb_get/put.
CC: Matthias Brugger
Signed-off-by: Yong Wu
Reviewed-by: Evan Green
---
drivers/memory/mtk-smi.c | 14
asz Figa
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c| 18 ++
drivers/iommu/mtk_iommu_v1.c | 20 +++-
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 7d8f3d0..5c3a6ba 100
ng up "mediatek,larb".
Signed-off-by: Maoguang Meng
Signed-off-by: Hsin-Yi Wang
Signed-off-by: Irui Wang
Signed-off-by: Yong Wu
---
.../devicetree/bindings/media/mediatek-vcodec.txt | 58 --
1 file changed, 31 insertions(+), 27 deletions(-)
diff --git a/Document
connects with from
iommu id in the "iommus=" property.
Signed-off-by: Yong Wu
Reviewed-by: Rob Herring
Reviewed-by: Evan Green
---
.../devicetree/bindings/display/mediatek/mediatek,disp.txt | 9 -
.../devicetree/bindings/media/mediatek-jpeg-decoder.txt | 4
Doc
consumer drivers run before
smi-larb, the supplier link_status is DL_DEV_NO_DRIVER(0) in the
device_link_add, then device_links_driver_bound will use WARN_ON
to complain that the link_status of supplier is not right.
This is a preparing patch for adding device_link.
Signed-off-by: Yong Wu
x again, resulting
> in a deadlock.
>
> As there is no reason why .probe_finalize() needs to be called under
> that mutex, move it after the lock has been released to fix the
> deadlock.
>
> Cc: Yong Wu
> Reported-by: Yong Wu
> Fixes: deac0b3bed26 ("iommu: Split off
On Fri, 2020-10-23 at 12:21 +0100, Will Deacon wrote:
> On Wed, Sep 30, 2020 at 03:06:34PM +0800, Yong Wu wrote:
> > The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
> > (4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
> > 34bit
On Fri, 2020-10-23 at 15:10 +0100, Robin Murphy wrote:
> On 2020-09-30 08:06, Yong Wu wrote:
> > The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
> > (4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
> > 34bit.
> >
On Fri, 2020-10-23 at 12:17 +0100, Will Deacon wrote:
> On Wed, Sep 30, 2020 at 03:06:31PM +0800, Yong Wu wrote:
> > Use the ias for the valid iova checking in arm_v7s_unmap. This is a
> > preparing patch for supporting iova 34bit for MediaTek.
> > BTW, change the ia
On Mon, 2020-07-27 at 16:49 +0800, chao hao wrote:
> On Sat, 2020-07-11 at 14:48 +0800, Yong Wu wrote:
> > In the previous SoC, the M4U HW is in the EMI power domain which is
> > always on. the latest M4U is in the display power domain which may be
> > turned on/off, thus we h
Hi Chao,
This is also ok for me. Only two format nitpick.
On Mon, 2020-06-29 at 15:13 +0800, Chao Hao wrote:
> Given the fact that we are adding more and more plat_data bool values,
> it would make sense to use a u32 flags register and add the appropriate
> macro definitions to set and check for
means subcommon_id above.
>
> We can also distinguish if the M4U HW has sub_common by HAS_SUB_COMM
> macro.
>
> Cc: Matthias Brugger
> Signed-off-by: Chao Hao
> Reviewed-by: Yong Wu
> ---
> drivers/iommu/mtk_iommu.c | 20 +---
> drivers/iommu/m
On Sun, 2020-07-12 at 20:06 +0200, Matthias Brugger wrote:
>
> On 11/07/2020 08:48, Yong Wu wrote:
> > Put all the macros about smi larb/port togethers, this is a preparing
> > patch for extending LARB_NR and adding new dom-id support.
> >
> > Signed-off-by: Y
On Mon, 2020-07-13 at 13:36 +0800, Pi-Hsun Shih wrote:
> On Sat, Jul 11, 2020 at 2:50 PM Yong Wu wrote:
> >
> > This patch adds decriptions for mt8192 IOMMU and SMI.
> >
> > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation
> > tab
On Mon, 2020-07-13 at 13:43 +0800, Pi-Hsun Shih wrote:
> On Mon, Jul 13, 2020 at 2:06 AM Matthias Brugger
> wrote:
> >
> >
> >
> > On 11/07/2020 08:48, Yong Wu wrote:
> > > Put all the macros about smi larb/port togethers, this is a preparing
> > >
On Mon, 2020-07-13 at 08:38 +0800, Nicolas Boichat wrote:
> On Sat, Jul 11, 2020 at 2:50 PM Yong Wu wrote:
> >
> > As title.
> >
> > Signed-off-by: Yong Wu
> > ---
> > drivers/iommu/io-pgtable-arm-v7s.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 d
On Mon, 2020-07-13 at 15:03 +0800, Pi-Hsun Shih wrote:
> On Sat, Jul 11, 2020 at 2:51 PM Yong Wu wrote:
> >
> > In the previous SoC, the M4U HW is in the EMI power domain which is
> > always on. the latest M4U is in the display power domain which may be
> > turned
On Mon, 2020-07-13 at 15:33 +0800, Pi-Hsun Shih wrote:
> On Sat, Jul 11, 2020 at 2:51 PM Yong Wu wrote:
> >
> > For multiple iommu_domains, we need to reserve some iova regions, so we
> > will add mtk_iommu_iova_region structure. It includes the base address
>
r each iommu-domain can't cross 4G.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 12 +---
drivers/memory/mtk-smi.c | 5 +
include/soc/mediatek/smi.h | 1 +
3 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
Defaultly the iova range is 0-4G. here we add a single-domain(0-4G)
for the previous SoC. this also is a preparing patch for supporting
multi-domains.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c
For multiple iommu_domains, we need to reserve some iova regions, so we
will add mtk_iommu_iova_region structure. It includes the base address
and size of the range.
This is a preparing patch for supporting multi-domain.
Signed-off-by: Anan sun
Signed-off-by: Hao Chao
Signed-off-by: Yong Wu
of macro '__AC'
#define _AC(X,Y) __AC(X,Y)
^
include/linux/sizes.h:46:18: note: in expansion of macro '_AC'
#define SZ_4G_AC(0x1, ULL)
Signed-off-by: Yong Wu
---
drivers/iommu/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/Kconfig b
If the iova is 34bit, the iova[32][33] is the bit0/1 in the tlb flush
register. Add a new macro for this.
there is a minor change unrelated with this patch. it also use the new
macro.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 10 ++
1 file changed, 6 insertions(+), 4
. if the power is off,
the main tlb will be reset while M4U power on, thus the tlb flush while
m4u power off is unnecessary, just skip it.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 54 ++-
1 file changed, 47 insertions(+), 7 deletions(-)
diff
Add mt8192 iommu support.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 20
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index a4ac41e60c4f..da7d055af919 100644
--- a/drivers
Add "struct mtk_iommu_data *" in the "struct mtk_iommu_domain",
reduce the call mtk_iommu_get_m4u_data().
No functional change.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drive
0x0 0x1 0x0 0x1 0x0>; /* 4G ~ 8G */
b) Update the dma_mask:
dma_set_mask_and_coherent(dev, DMA_BIT_MASK(33));
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 49 ---
drivers/iommu/mtk_iommu.h | 3 ++-
2 files changed, 42 insertions(+), 10 deletions(-)
Add mt8192 smi support.
Signed-off-by: Yong Wu
---
drivers/memory/mtk-smi.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index f2f6100c74ef..5d0268630e70 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory
If the iova is over 32bit, the fault status register bit is a little
different. Add a flag for the special register bits.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b
Put all the macros about smi larb/port togethers, this is a preparing
patch for extending LARB_NR and adding new dom-id support.
Signed-off-by: Yong Wu
---
include/dt-bindings/memory/mt2712-larb-port.h | 2 +-
include/dt-bindings/memory/mt6779-larb-port.h | 2 +-
include/dt-bindings/memory
The standard input iova bits is 32. MediaTek quad the lvl1
pagetable(4*lvl1). No change for lvl2 pagetable.
Then the iova bits can reach 34bit.
Signed-off-by: Yong Wu
---
drivers/iommu/io-pgtable-arm-v7s.c | 10 +++---
drivers/iommu/mtk_iommu.c | 2 +-
2 files changed, 8
for multi-domain support.
Signed-off-by: Yong Wu
---
include/dt-bindings/memory/mtk-smi-larb-port.h | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/memory/mtk-smi-larb-port.h
b/include/dt-bindings/memory/mtk-smi-larb-port.h
index f4d8e3aed0bc
4 CCU10x4400_ ~ 0x47ff_ larb14: port 4/5
The iova range for CCU0/1(camera control unit) is HW requirement.
Signed-off-by: Yong Wu
---
.../bindings/iommu/mediatek,iommu.txt | 8 +-
.../mediatek,smi-common.txt | 5 +-
.../memory-controllers
Add "cfg" as a parameter for some macros. This is a preparing patch for
mediatek extend the lvl1 pgtable. No functional change.
Signed-off-by: Yong Wu
---
drivers/iommu/io-pgtable-arm-v7s.c | 34 +++---
1 file changed, 17 insertions(+), 17 deletions(-)
-common power is enabled, the M4U power also is powered on
automatically.
In this patch, a M4U connects with several smi-larbs and their smi-common
always are the same, thus it adds the device-link once is enough.
And the devicelink only is needed while m4u has power-domain.
Signed-off-by: Yong Wu
Extend the max larb number definition as mt8192 has larb_nr over 16.
Signed-off-by: Yong Wu
---
include/dt-bindings/memory/mtk-smi-larb-port.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/dt-bindings/memory/mtk-smi-larb-port.h
b/include/dt-bindings/memory/mtk
Use the common larb-port header in the source code.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 7 ---
drivers/iommu/mtk_iommu.h | 1 +
drivers/memory/mtk-smi.c | 1 +
include/soc/mediatek/smi.h | 2 --
4 files changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers
domains support since several HW has the special iova
region requirement.
this patchset depend on v5.8-rc1 and mt6779 iommu[1].
[1]https://lore.kernel.org/linux-iommu/20200703044127.27438-1-chao@mediatek.com/
Yong Wu (21):
dt-binding: memory: mediatek: Add a common larb-port header file
dt
As title.
Signed-off-by: Yong Wu
---
drivers/iommu/io-pgtable-arm-v7s.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c
b/drivers/iommu/io-pgtable-arm-v7s.c
index 4272fe4e17f4..01f2a8876808 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
MediaTek extend the bit5 in lvl1 and lvl2 descriptor as PA34.
Signed-off-by: Yong Wu
---
drivers/iommu/io-pgtable-arm-v7s.c | 9 +++--
drivers/iommu/mtk_iommu.c | 2 +-
include/linux/io-pgtable.h | 4 ++--
3 files changed, 10 insertions(+), 5 deletions(-)
diff --git
n. So rename REG_MMU_MISC_CTRL may be more proper.
>
> This patch only rename the register name, no functional change.
>
> Signed-off-by: Chao Hao
> Reviewed-by: Yong Wu
> Reviewed-by: Matthias Brugger
> ---
> drivers/iommu/mtk_iommu.c | 14 +++---
> drive
On Fri, 2020-07-10 at 16:13 +0200, Joerg Roedel wrote:
> On Fri, Jul 03, 2020 at 12:41:17PM +0800, Chao Hao wrote:
> > Chao Hao (10):
> > dt-bindings: mediatek: Add bindings for MT6779
> > iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL
> > iommu/mediatek: Use a u32
<-sub_common_id(max is 4)
> > || | |
> >Larb8Larb9 Larb10 Larb11
> >
> > In this patch we extern larb_remap[] to larb_remap[8][4] for this.
>
> extern -> extend
>
> > larb_remap[x][y]: x mean common-id above,
+ Rick
On Sat, 2020-05-30 at 16:10 +0800, Yong Wu wrote:
> MediaTek IOMMU has already added device_link between the consumer
> and smi-larb device. If the jpg device call the pm_runtime_get_sync,
> the smi-larb's pm_runtime_get_sync also be called automatically.
>
> CC: Rick Chan
Hi Chao,
On Thu, 2020-06-18 at 19:49 +0800, chao hao wrote:
> On Wed, 2020-06-17 at 11:34 +0200, Matthias Brugger wrote:
[snip]
> > >
> > > #define REG_MMU_MISC_CTRL0x048
> > > +#define F_MMU_IN_ORDER_WR_EN (BIT(1) | BIT(17))
> > > +#define
On Thu, 2020-07-23 at 14:47 -0600, Rob Herring wrote:
> On Sat, Jul 11, 2020 at 02:48:43PM +0800, Yong Wu wrote:
> > Some HW IP(ex: CCU) require the special iova range. That means the
> > iova got from dma_alloc_attrs for that devices must locate in his
> > special ran
On Mon, 2020-07-20 at 17:16 -0600, Rob Herring wrote:
> On Sat, Jul 11, 2020 at 02:48:29PM +0800, Yong Wu wrote:
> > This patch adds decriptions for mt8192 IOMMU and SMI.
> >
> > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation
> > table for
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