Re: [PATCH v4 6/7] iommu/mediatek: Add REG_MMU_WR_LEN definition preparing for mt6779

On Wed, 2020-06-17 at 11:22 +0200, Matthias Brugger wrote: > > On 17/06/2020 05:00, Chao Hao wrote: > > Some platforms(ex: mt6779) have a new register called by REG_MMU_WR_LEN > > to improve performance. > > This patch add this register definition. > > Please be mo

Re: [PATCH v4 7/7] iommu/mediatek: Add mt6779 basic support

On Thu, 2020-06-18 at 18:00 +0200, Matthias Brugger wrote: > > On 18/06/2020 13:54, chao hao wrote: > > On Wed, 2020-06-17 at 11:33 +0200, Matthias Brugger wrote: > >> > >> On 17/06/2020 05:00, Chao Hao wrote: > >>> 1. Start from mt6779,

Re: [PATCH v4 6/7] iommu/mediatek: Add REG_MMU_WR_LEN definition preparing for mt6779

On Sun, 2020-06-21 at 13:01 +0200, Matthias Brugger wrote: > > On 19/06/2020 12:56, chao hao wrote: > > On Wed, 2020-06-17 at 11:22 +0200, Matthias Brugger wrote: > >> > >> On 17/06/2020 05:00, Chao Hao wrote: > >>> Some platforms(ex: mt6779) ha

Re: [PATCH v4 3/7] iommu/mediatek: Set MISC_CTRL register

On Sat, 2020-06-20 at 10:03 +0800, Yong Wu wrote: > Hi Chao, > > On Thu, 2020-06-18 at 19:49 +0800, chao hao wrote: > > On Wed, 2020-06-17 at 11:34 +0200, Matthias Brugger wrote: > > [snip] > > > > > > > > > #define REG_MMU_MISC_

[PATCH v5 05/10] iommu/mediatek: Move inv_sel_reg into the plat_data

For mt6779, MMU_INV_SEL register's offset is changed from 0x38 to 0x2c, so we can put inv_sel_reg in the plat_data to use it. In addition, we renamed it to REG_MMU_INV_SEL_GEN1 and use it before mt6779. Cc: Yong Wu Signed-off-by: Chao Hao Reviewed-by: Matthias Brugger --- drivers/iommu

[PATCH v5 07/10] iommu/mediatek: Add REG_MMU_WR_LEN register definition

-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 10 ++ drivers/iommu/mtk_iommu.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index ec1f86913739..92316c4175a9 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu

[PATCH v5 01/10] dt-bindings: mediatek: Add bindings for MT6779

) || ||| || -- || | | | Multimedia engine CCU VPU MDLA EMDA All the connections are hardware fixed, software can not adjust it. Signed-off-by: Chao Hao Reviewed-by: Rob

[PATCH v5 09/10] iommu/mediatek: Modify MMU_CTRL register setting

_ADDR", victim_tlb will be disabled, it will drop iommu performace. So we need to deal with the setting of MMU_CTRL separately for mt8173 and others. Suggested-by: Matthias Brugger Suggested-by: Yong Wu Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 3 ++- 1 file changed, 2 insertions(+),

[PATCH v5 00/10] MT6779 IOMMU SUPPORT

. 5. Split "iommu/mediatek: Add mt6779 IOMMU basic support(patch v1)" to several patches(patch v2). http://lists.infradead.org/pipermail/linux-mediatek/2020-January/026131.html v1: http://lists.infradead.org/pipermail/linux-mediatek/2019-November/024567.html Chao Hao (10): dt-bi

[PATCH v5 03/10] iommu/mediatek: Modify the usage of mtk_iommu_plat_data structure

Given the fact that we are adding more and more plat_data bool values, it would make sense to use a u32 flags register and add the appropriate macro definitions to set and check for a flag present. No functional change. Suggested-by: Matthias Brugger Signed-off-by: Chao Hao --- drivers/iommu

[PATCH v5 06/10] iommu/mediatek: Add sub_comm id in translation fault

we extend larb_remap[] to larb_remap[8][4] for this. larb_remap[x][y]: x means common-id above, y means subcommon_id above. We can also distinguish if the M4U HW has sub_common by HAS_SUB_COMM macro. Cc: Matthias Brugger Signed-off-by: Chao Hao Reviewed-by: Yong Wu --- drivers/iommu/mtk_iomm

[PATCH v5 08/10] iommu/mediatek: Extend protect pa alignment value

Starting with mt6779, iommu needs to extend to 256 bytes from 128 bytes which can send the max number of data for memory protection pa alignment. So we can use a separate patch to modify it. Suggested-by: Matthias Brugger Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 2 +- 1 file

[PATCH v5 04/10] iommu/mediatek: Setting MISC_CTRL register

Brugger Suggested-by: Yong Wu Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 12 +++- drivers/iommu/mtk_iommu.h | 1 + 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 8f81df6cbe51..67b46b5d83d9 100644

[PATCH v5 10/10] iommu/mediatek: Add mt6779 basic support

1. Start from mt6779, INVLDT_SEL move to offset=0x2c, so we add REG_MMU_INV_SEL_GEN2 definition and mt6779 uses it. 2. Add mt6779_data to support mm_iommu HW init. Cc: Yong Wu Cc: Matthias Brugger Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 11 +++ drivers/iommu

[PATCH v5 02/10] iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL

the register name, no functional change. Signed-off-by: Chao Hao Reviewed-by: Yong Wu Reviewed-by: Matthias Brugger --- drivers/iommu/mtk_iommu.c | 14 +++--- drivers/iommu/mtk_iommu.h | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b

Re: [PATCH 11/21] iommu/mediatek: Add power-domain operation

On Sat, 2020-07-11 at 14:48 +0800, Yong Wu wrote: > In the previous SoC, the M4U HW is in the EMI power domain which is > always on. the latest M4U is in the display power domain which may be > turned on/off, thus we have to add pm_runtime interface for it. > > we should enable its power before

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