Re: [Devel] [RESEND PATCH v9 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126

2017-06-27 Thread Geetha Akula
On Tue, Jun 27, 2017 at 7:36 PM, Will Deacon wrote: > On Tue, Jun 27, 2017 at 03:56:10PM +0200, Robert Richter wrote: >> On 23.06.17 19:04:36, Geetha sowjanya wrote: >> > From: Geetha Sowjanya >> > >> > Cavium ThunderX2 SMMU doesn't support

Re: [PATCH v9 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126

2017-06-23 Thread Geetha Akula
On Thu, Jun 22, 2017 at 11:52 PM, Will Deacon wrote: > Hi Geetha, > > On Thu, Jun 22, 2017 at 05:35:38PM +0530, Geetha sowjanya wrote: >> From: Geetha Sowjanya >> >> Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq

Re: [PATCH v8 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126

2017-06-21 Thread Geetha Akula
Hi Will, On Tue, Jun 20, 2017 at 11:30 PM, Will Deacon wrote: > On Tue, Jun 20, 2017 at 07:47:39PM +0530, Geetha sowjanya wrote: >> From: Geetha Sowjanya >> >> Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq >>

Re: [PATCH v7 1/3] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model

2017-06-09 Thread Geetha Akula
On Thu, Jun 8, 2017 at 2:28 PM, Lorenzo Pieralisi wrote: > On Tue, May 30, 2017 at 05:33:39PM +0530, Geetha sowjanya wrote: >> From: Linu Cherian >> >> Cavium ThunderX2 implementation doesn't support second page in SMMU >> register space.

Re: [v6 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

2017-05-18 Thread Geetha Akula
On Tue, May 16, 2017 at 5:45 AM, Rob Herring wrote: > DT changes should go to DT list. > > On Fri, May 12, 2017 at 7:41 AM, Geetha sowjanya > wrote: >> From: Linu Cherian >> >> Cavium ThunderX2 SMMU implementation doesn't

Re: [v6 1/3] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model

2017-05-12 Thread Geetha Akula
On Sat, May 13, 2017 at 6:03 AM, kbuild test robot wrote: > Hi Linu, > > [auto build test ERROR on arm64/for-next/core] > [also build test ERROR on v4.11 next-20170512] > [if your patch is applied to the wrong git tree, please drop us a note to > help improve the system] > > url:

Re: [v5 1/4] ACPICA: IORT: Add Cavium ThunderX2 SMMUv3 model definition.

2017-05-12 Thread Geetha Akula
On Fri, May 12, 2017 at 3:54 PM, Will Deacon wrote: > On Thu, May 11, 2017 at 04:40:51PM +0200, Rafael J. Wysocki wrote: >> On Thursday, May 11, 2017 09:45:25 AM Will Deacon wrote: >> > On Thu, May 11, 2017 at 02:26:02AM +0200, Rafael J. Wysocki wrote: >> > > On Wednesday,

Re: [PATCH v3 6/7] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126

2017-05-08 Thread Geetha Akula
On Mon, May 8, 2017 at 4:51 PM, Robin Murphy wrote: > On 05/05/17 13:08, Geetha sowjanya wrote: >> From: Geetha Sowjanya >> >> Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq >> lines for gerror, eventq and

Re: [PATCH v3 2/7] iommu/arm-smmu-v3: Do resource size checks based on SMMU

2017-05-08 Thread Geetha Akula
On Mon, May 8, 2017 at 3:39 PM, Robert Richter wrote: > On 08.05.17 15:14:37, Linu Cherian wrote: >> On Sat May 06, 2017 at 12:18:44AM +0200, Robert Richter wrote: >> > On 05.05.17 17:38:06, Geetha sowjanya wrote: >> > > From: Linu Cherian >> >

Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

2017-05-05 Thread Geetha Akula
t;j...@jonmasters.org> wrote: > On 05/03/2017 05:47 AM, Will Deacon wrote: > > Hi Geetha, > > > > On Tue, May 02, 2017 at 12:01:15PM +0530, Geetha Akula wrote: > >> SMMU_IIDR register is broken on T99, that the reason we are using MIDR. > > > > Urgh, that's unfortun

Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

2017-05-03 Thread Geetha Akula
Hi Will, We will resubmit the patches based on IORT. Thank you, Geetha. On Wed, May 3, 2017 at 3:17 PM, Will Deacon <will.dea...@arm.com> wrote: > Hi Geetha, > > On Tue, May 02, 2017 at 12:01:15PM +0530, Geetha Akula wrote: >> SMMU_IIDR register is broken on T99, that th

Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

2017-05-02 Thread Geetha Akula
Hi Will, SMMU_IIDR register is broken on T99, that the reason we are using MIDR. If using MIDR is not accepted, can we enable errata based on SMMU resource size? some thing like below. static bool page0_reg_only = false; +static unsigned long arm_smmu_resource_size(void) +{ + if

Re: [RFC v4 15/16] vfio/type1: Check MSI remapping at irq domain level

2016-12-23 Thread Geetha Akula
Hi Eric, Seeing same issue reported by Diana on ThunderX with you v4.9-reserved-v4 branch. Vfio passthough work fine when allow_unsafe_interrupts is set. Thank you, Geetha. On Thu, Dec 22, 2016 at 6:32 PM, Auger Eric wrote: > Hi Diana, > > On 22/12/2016 13:41, Diana