Re: [PATCH v6 11/25] iommu/arm-smmu-v3: Share process page tables

2020-05-04 Thread Suzuki K Poulose 

On 05/04/2020 03:11 PM, Jean-Philippe Brucker wrote:

On Thu, Apr 30, 2020 at 04:39:53PM +0100, Suzuki K Poulose wrote:

On 04/30/2020 03:34 PM, Jean-Philippe Brucker wrote:

With Shared Virtual Addressing (SVA), we need to mirror CPU TTBR, TCR,
MAIR and ASIDs in SMMU contexts. Each SMMU has a single ASID space split
into two sets, shared and private. Shared ASIDs correspond to those
obtained from the arch ASID allocator, and private ASIDs are used for
"classic" map/unmap DMA.

Cc: Suzuki K Poulose 
Signed-off-by: Jean-Philippe Brucker 
---



+
+   tcr = FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, 64ULL - VA_BITS) |
+ FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, ARM_LPAE_TCR_RGN_WBWA) |
+ FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, ARM_LPAE_TCR_RGN_WBWA) |
+ FIELD_PREP(CTXDESC_CD_0_TCR_SH0, ARM_LPAE_TCR_SH_IS) |
+ CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64;
+
+   switch (PAGE_SIZE) {
+   case SZ_4K:
+   tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_4K);
+   break;
+   case SZ_16K:
+   tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_16K);
+   break;
+   case SZ_64K:
+   tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_64K);
+   break;
+   default:
+   WARN_ON(1);
+   ret = -EINVAL;
+   goto err_free_asid;
+   }
+
+   reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
+   par = cpuid_feature_extract_unsigned_field(reg, 
ID_AA64MMFR0_PARANGE_SHIFT);
+   tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_IPS, par);
+
+   cd->ttbr = virt_to_phys(mm->pgd);


Does the TTBR follow the same layout as TTBR_ELx for 52bit IPA ? i.e,
TTBR[5:2] = BADDR[51:48] ? Are you covered for that ?


Good point, I don't remember checking this. The SMMU TTBR doesn't have the
same layout as the CPU's, and we don't need to swizzle the bits. For the
lower bits, the alignment requirements on the pgd are identical to the
MMU.


Ok, if that is the case:

Acked-by: Suzuki K Poulose 
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Re: [PATCH v6 11/25] iommu/arm-smmu-v3: Share process page tables

2020-04-30 Thread Suzuki K Poulose 

On 04/30/2020 03:34 PM, Jean-Philippe Brucker wrote:

With Shared Virtual Addressing (SVA), we need to mirror CPU TTBR, TCR,
MAIR and ASIDs in SMMU contexts. Each SMMU has a single ASID space split
into two sets, shared and private. Shared ASIDs correspond to those
obtained from the arch ASID allocator, and private ASIDs are used for
"classic" map/unmap DMA.

Cc: Suzuki K Poulose 
Signed-off-by: Jean-Philippe Brucker 
---



+
+   tcr = FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, 64ULL - VA_BITS) |
+ FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, ARM_LPAE_TCR_RGN_WBWA) |
+ FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, ARM_LPAE_TCR_RGN_WBWA) |
+ FIELD_PREP(CTXDESC_CD_0_TCR_SH0, ARM_LPAE_TCR_SH_IS) |
+ CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64;
+
+   switch (PAGE_SIZE) {
+   case SZ_4K:
+   tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_4K);
+   break;
+   case SZ_16K:
+   tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_16K);
+   break;
+   case SZ_64K:
+   tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_64K);
+   break;
+   default:
+   WARN_ON(1);
+   ret = -EINVAL;
+   goto err_free_asid;
+   }
+
+   reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
+   par = cpuid_feature_extract_unsigned_field(reg, 
ID_AA64MMFR0_PARANGE_SHIFT);
+   tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_IPS, par);
+
+   cd->ttbr = virt_to_phys(mm->pgd);


Does the TTBR follow the same layout as TTBR_ELx for 52bit IPA ? i.e, 
TTBR[5:2] = BADDR[51:48] ? Are you covered for that ?


Suzuki
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Re: [PATCH v6 10/25] arm64: cpufeature: Export symbol read_sanitised_ftr_reg()

2020-04-30 Thread Suzuki K Poulose 

On 04/30/2020 03:34 PM, Jean-Philippe Brucker wrote:

The SMMUv3 driver would like to read the MMFR0 PARANGE field in order to
share CPU page tables with devices. Allow the driver to be built as
module by exporting the read_sanitized_ftr_reg() cpufeature symbol.

Cc: Suzuki K Poulose 
Signed-off-by: Jean-Philippe Brucker 


Acked-by: Suzuki K Poulose 


---
  arch/arm64/kernel/cpufeature.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 9fac745aa7bb2..5f6adbf4ae893 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -841,6 +841,7 @@ u64 read_sanitised_ftr_reg(u32 id)
BUG_ON(!regp);
return regp->sys_val;
  }
+EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
  
  #define read_sysreg_case(r)	\

case r: return read_sysreg_s(r)



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