Re: [PATCH v5 01/20] dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI
Hi Evan, Thanks very much for reviewing this patchset. On Wed, 2019-01-30 at 10:27 -0800, Evan Green wrote: > On Mon, Dec 31, 2018 at 7:56 PM Yong Wu wrote: > > > > This patch adds decriptions for mt8183 IOMMU and SMI. > > > > mt8183 has only one M4U like mt8173 and is also MTK IOMMU gen2 which > > uses ARM Short-Descriptor translation table format. > > > > The mt8183 M4U-SMI HW diagram is as below: > > > > EMI > >| > > M4U > >| > >-- > >|| > >gals0-rx gals1-rx > >|| > >|| > >gals0-tx gals1-tx > >|| > > > >SMI Common > > > >| > > +-+-++-+-+---+---+ > > | | || | | | | > > | | gals-rx gals-rx | gals-rx gals-rx gals-rx > > | | || | | | | > > | | || | | | | > > | | gals-tx gals-tx | gals-tx gals-tx gals-tx > > | | || | | | | > > larb0 larb1 IPU0IPU1 larb4 larb5 larb6CCU > > disp vdec img camvenc imgcam > > It might be cool to put the gals in the picture in the bindings. Not a > big deal though. OK. the picture in the binding should be more generic, I will try add gals in the binding picture in next version. > > > > > All the connections are HW fixed, SW can NOT adjust it. > > > > Compared with mt8173, we add a GALS(Global Async Local Sync) module > > between SMI-common and M4U, and additional GALS between larb2/3/5/6 > > and SMI-common. GALS can help synchronize for the modules in different > > clock frequency, it can be seen as a "asynchronous fifo". > > > > GALS can only help transfer the command/data while it doesn't have > > the configuring register, thus it has the special "smi" clock and it > > doesn't have the "apb" clock. From the diagram above, we add "gals0" > > and "gals1" clocks for smi-common and add a "gals" clock for smi-larb. > > > > From the diagram above, IPU0/IPU1(Image Processor Unit) and CCU(Camera > > Control Unit) is connected with smi-common directly, we can take them > > as "larb2", "larb3" and "larb7", and their register spaces are > > different with the normal larb. > > > > Signed-off-by: Yong Wu > > Reviewed-by: Rob Herring > > --- > > .../devicetree/bindings/iommu/mediatek,iommu.txt | 15 ++- > > .../memory-controllers/mediatek,smi-common.txt | 11 +- > > .../memory-controllers/mediatek,smi-larb.txt | 3 + > > include/dt-bindings/memory/mt8183-larb-port.h | 130 > > + > > 4 files changed, 153 insertions(+), 6 deletions(-) > > create mode 100644 include/dt-bindings/memory/mt8183-larb-port.h > > > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > index 6922db5..6e758996 100644 > > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > @@ -36,6 +36,10 @@ each local arbiter. > > like display, video decode, and camera. And there are different ports > > in each larb. Take a example, There are many ports like MC, PP, VLD in the > > video decode local arbiter, all these ports are according to the video HW. > > + In some SoCs, there may be a GALS(Global Async Local Sync) module between > > +smi-common and m4u, and additional GALS module between smi-larb and > > +smi-common. GALS can been seen as a "asynchronous fifo" which could help > > +synchronize for the modules in different clock frequency. > > > > Required properties: > > - compatible : must be one of the following string: > > @@ -44,18 +48,23 @@ Required properties: > > "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses > > generation one m4u HW. > > "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. > > + "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW. > > - reg : m4u register base and size. > > - interrupts : the interrupt of m4u. > > - clocks : must contain one entry for each clock-names. > > -- clock-names : must be "bclk", It is the block clock of m4u. > > +- clock-names : Only 1 optional clock: > > + - "bclk": the block clock of m4u. > > + Note that m4u use the EMI clock which always has been enabled before > > kernel > > + if there is no this "bclk". > > Ideally bclk could be specified a little more crisply, as this is > actually required for some SoCs and not used at all on others (as in > patch 7). OK.
Re: [PATCH v5 01/20] dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI
On Mon, Dec 31, 2018 at 7:56 PM Yong Wu wrote: > > This patch adds decriptions for mt8183 IOMMU and SMI. > > mt8183 has only one M4U like mt8173 and is also MTK IOMMU gen2 which > uses ARM Short-Descriptor translation table format. > > The mt8183 M4U-SMI HW diagram is as below: > > EMI >| > M4U >| >-- >|| >gals0-rx gals1-rx >|| >|| >gals0-tx gals1-tx >|| > >SMI Common > >| > +-+-++-+-+---+---+ > | | || | | | | > | | gals-rx gals-rx | gals-rx gals-rx gals-rx > | | || | | | | > | | || | | | | > | | gals-tx gals-tx | gals-tx gals-tx gals-tx > | | || | | | | > larb0 larb1 IPU0IPU1 larb4 larb5 larb6CCU > disp vdec img camvenc imgcam It might be cool to put the gals in the picture in the bindings. Not a big deal though. > > All the connections are HW fixed, SW can NOT adjust it. > > Compared with mt8173, we add a GALS(Global Async Local Sync) module > between SMI-common and M4U, and additional GALS between larb2/3/5/6 > and SMI-common. GALS can help synchronize for the modules in different > clock frequency, it can be seen as a "asynchronous fifo". > > GALS can only help transfer the command/data while it doesn't have > the configuring register, thus it has the special "smi" clock and it > doesn't have the "apb" clock. From the diagram above, we add "gals0" > and "gals1" clocks for smi-common and add a "gals" clock for smi-larb. > > From the diagram above, IPU0/IPU1(Image Processor Unit) and CCU(Camera > Control Unit) is connected with smi-common directly, we can take them > as "larb2", "larb3" and "larb7", and their register spaces are > different with the normal larb. > > Signed-off-by: Yong Wu > Reviewed-by: Rob Herring > --- > .../devicetree/bindings/iommu/mediatek,iommu.txt | 15 ++- > .../memory-controllers/mediatek,smi-common.txt | 11 +- > .../memory-controllers/mediatek,smi-larb.txt | 3 + > include/dt-bindings/memory/mt8183-larb-port.h | 130 > + > 4 files changed, 153 insertions(+), 6 deletions(-) > create mode 100644 include/dt-bindings/memory/mt8183-larb-port.h > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > index 6922db5..6e758996 100644 > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > @@ -36,6 +36,10 @@ each local arbiter. > like display, video decode, and camera. And there are different ports > in each larb. Take a example, There are many ports like MC, PP, VLD in the > video decode local arbiter, all these ports are according to the video HW. > + In some SoCs, there may be a GALS(Global Async Local Sync) module between > +smi-common and m4u, and additional GALS module between smi-larb and > +smi-common. GALS can been seen as a "asynchronous fifo" which could help > +synchronize for the modules in different clock frequency. > > Required properties: > - compatible : must be one of the following string: > @@ -44,18 +48,23 @@ Required properties: > "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses > generation one m4u HW. > "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. > + "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW. > - reg : m4u register base and size. > - interrupts : the interrupt of m4u. > - clocks : must contain one entry for each clock-names. > -- clock-names : must be "bclk", It is the block clock of m4u. > +- clock-names : Only 1 optional clock: > + - "bclk": the block clock of m4u. > + Note that m4u use the EMI clock which always has been enabled before kernel > + if there is no this "bclk". Ideally bclk could be specified a little more crisply, as this is actually required for some SoCs and not used at all on others (as in patch 7). > - mediatek,larbs : List of phandle to the local arbiters in the current Socs. > Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must > sort > according to the local arbiter index, like larb0, larb1, larb2... > - iommu-cells : must be 1. This is the mtk_m4u_id according to the HW. > Specifies the mtk_m4u_id as defined in > dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623 >
[PATCH v5 01/20] dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI
This patch adds decriptions for mt8183 IOMMU and SMI.
mt8183 has only one M4U like mt8173 and is also MTK IOMMU gen2 which
uses ARM Short-Descriptor translation table format.
The mt8183 M4U-SMI HW diagram is as below:
EMI
|
M4U
|
--
||
gals0-rx gals1-rx
||
||
gals0-tx gals1-tx
||
SMI Common
|
+-+-++-+-+---+---+
| | || | | | |
| | gals-rx gals-rx | gals-rx gals-rx gals-rx
| | || | | | |
| | || | | | |
| | gals-tx gals-tx | gals-tx gals-tx gals-tx
| | || | | | |
larb0 larb1 IPU0IPU1 larb4 larb5 larb6CCU
disp vdec img camvenc imgcam
All the connections are HW fixed, SW can NOT adjust it.
Compared with mt8173, we add a GALS(Global Async Local Sync) module
between SMI-common and M4U, and additional GALS between larb2/3/5/6
and SMI-common. GALS can help synchronize for the modules in different
clock frequency, it can be seen as a "asynchronous fifo".
GALS can only help transfer the command/data while it doesn't have
the configuring register, thus it has the special "smi" clock and it
doesn't have the "apb" clock. From the diagram above, we add "gals0"
and "gals1" clocks for smi-common and add a "gals" clock for smi-larb.
>From the diagram above, IPU0/IPU1(Image Processor Unit) and CCU(Camera
Control Unit) is connected with smi-common directly, we can take them
as "larb2", "larb3" and "larb7", and their register spaces are
different with the normal larb.
Signed-off-by: Yong Wu
Reviewed-by: Rob Herring
---
.../devicetree/bindings/iommu/mediatek,iommu.txt | 15 ++-
.../memory-controllers/mediatek,smi-common.txt | 11 +-
.../memory-controllers/mediatek,smi-larb.txt | 3 +
include/dt-bindings/memory/mt8183-larb-port.h | 130 +
4 files changed, 153 insertions(+), 6 deletions(-)
create mode 100644 include/dt-bindings/memory/mt8183-larb-port.h
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
index 6922db5..6e758996 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
@@ -36,6 +36,10 @@ each local arbiter.
like display, video decode, and camera. And there are different ports
in each larb. Take a example, There are many ports like MC, PP, VLD in the
video decode local arbiter, all these ports are according to the video HW.
+ In some SoCs, there may be a GALS(Global Async Local Sync) module between
+smi-common and m4u, and additional GALS module between smi-larb and
+smi-common. GALS can been seen as a "asynchronous fifo" which could help
+synchronize for the modules in different clock frequency.
Required properties:
- compatible : must be one of the following string:
@@ -44,18 +48,23 @@ Required properties:
"mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses
generation one m4u HW.
"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
+ "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW.
- reg : m4u register base and size.
- interrupts : the interrupt of m4u.
- clocks : must contain one entry for each clock-names.
-- clock-names : must be "bclk", It is the block clock of m4u.
+- clock-names : Only 1 optional clock:
+ - "bclk": the block clock of m4u.
+ Note that m4u use the EMI clock which always has been enabled before kernel
+ if there is no this "bclk".
- mediatek,larbs : List of phandle to the local arbiters in the current Socs.
Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort
according to the local arbiter index, like larb0, larb1, larb2...
- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
Specifies the mtk_m4u_id as defined in
dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623
- dt-binding/memory/mt2712-larb-port.h for mt2712, and
- dt-binding/memory/mt8173-larb-port.h for mt8173.
+ dt-binding/memory/mt2712-larb-port.h for mt2712,
+ dt-binding/memory/mt8173-larb-port.h for mt8173, and
+ dt-binding/memory/mt8183-larb-port.h for mt8183.
Example:
iommu: iommu@10205000 {
diff --git
a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
