Re: [PATCH] iommu/arm-smmu: clear cache lock bit of ACR

Hi Robin, On Tue, May 03, 2016 at 12:15:52PM +0100, Robin Murphy wrote: >On 03/05/16 11:15, Peng Fan wrote: >>According MMU-500 TRM, section 3.7.1 Auxiliary Control registers, >>You can modify ACTLR only when the ACR.CACHE_LOCK bit is 0. >> >>So before clearing ARM_MMU500_ACTLR_CPRE of each

Re: [PATCH] iommu/arm-smmu: clear cache lock bit of ACR

On 03/05/16 11:15, Peng Fan wrote: According MMU-500 TRM, section 3.7.1 Auxiliary Control registers, You can modify ACTLR only when the ACR.CACHE_LOCK bit is 0. So before clearing ARM_MMU500_ACTLR_CPRE of each context bank, need clear CACHE_LOCK bit of ACR register first. Ah, good catch - I

[PATCH] iommu/arm-smmu: clear cache lock bit of ACR

According MMU-500 TRM, section 3.7.1 Auxiliary Control registers, You can modify ACTLR only when the ACR.CACHE_LOCK bit is 0. So before clearing ARM_MMU500_ACTLR_CPRE of each context bank, need clear CACHE_LOCK bit of ACR register first. Signed-off-by: Peng Fan Cc: Will