Re: [PATCH] iommu/vt-d: Fix intel_pasid_max_id

2019-04-30 Thread Auger Eric
Hi Jacob, On 4/30/19 8:01 PM, Jacob Pan wrote: > On Tue, 30 Apr 2019 09:29:40 +0200 > Eric Auger wrote: > >> Extended Capability Register PSS field (PASID Size Supported) >> corresponds to the PASID bit size -1. >> >> "A value of N in this field indicates hardware supports PASID >> field of N+1

Re: [PATCH] iommu/vt-d: Fix intel_pasid_max_id

2019-04-30 Thread Jacob Pan
On Tue, 30 Apr 2019 09:29:40 +0200 Eric Auger wrote: > Extended Capability Register PSS field (PASID Size Supported) > corresponds to the PASID bit size -1. > > "A value of N in this field indicates hardware supports PASID > field of N+1 bits (For example, value of 7 in this field, > indicates

[PATCH] iommu/vt-d: Fix intel_pasid_max_id

2019-04-30 Thread Eric Auger
Extended Capability Register PSS field (PASID Size Supported) corresponds to the PASID bit size -1. "A value of N in this field indicates hardware supports PASID field of N+1 bits (For example, value of 7 in this field, indicates 8-bit PASIDs are supported)". Fix the computation of