On Fri, 22 Jan 2021 09:51:20 +0100
Jean-Philippe Brucker wrote:
> On Thu, Jan 21, 2021 at 07:12:36PM +, Jonathan Cameron wrote:
> > > @@ -2502,6 +2647,7 @@ static void arm_smmu_release_device(struct device
> > > *dev)
> > >
> > > master = dev_iommu_priv_get(dev);
> > >
On Thu, Jan 21, 2021 at 07:12:36PM +, Jonathan Cameron wrote:
> > @@ -2502,6 +2647,7 @@ static void arm_smmu_release_device(struct device
> > *dev)
> >
> > master = dev_iommu_priv_get(dev);
> > WARN_ON(arm_smmu_master_sva_enabled(master));
> > +
On Thu, 21 Jan 2021 13:36:24 +0100
Jean-Philippe Brucker wrote:
> The SMMU provides a Stall model for handling page faults in platform
> devices. It is similar to PCIe PRI, but doesn't require devices to have
> their own translation cache. Instead, faulting transactions are parked
> and the OS
The SMMU provides a Stall model for handling page faults in platform
devices. It is similar to PCIe PRI, but doesn't require devices to have
their own translation cache. Instead, faulting transactions are parked
and the OS is given a chance to fix the page tables and retry the
transaction.
Enable
