On Mon, Apr 28, 2014 at 02:05:30PM +0200, Arnd Bergmann wrote:
[...]
let me clarify by example:
iommu@1 {
compatible = some,simple-iommu;
reg = 1;
#iommu-cells = 0; /* supports only one master */
};
iommu@2 {
On Thu, 15 May 2014 22:37:31 +0200, Thierry Reding wrote:
On Mon, Apr 28, 2014 at 02:05:30PM +0200, Arnd Bergmann wrote:
[...]
let me clarify by example:
iommu@1 {
compatible = some,simple-iommu;
reg = 1;
#iommu-cells = 0; /* supports only one
On Thu, May 01, 2014 at 06:41:37PM +0100, Stephen Warren wrote:
On 04/29/2014 03:00 PM, Arnd Bergmann wrote:
...
Yes. It's very complicated unfortunately, because we have to be
able to deal with arbitrary combinations of a lot of oddball cases
that can show up in random SoCs:
...
- a
On Tue, Apr 29, 2014 at 10:46:18PM +0200, Arnd Bergmann wrote:
On Tuesday 29 April 2014 19:16:02 Dave Martin wrote:
[...]
For example, suppose devices can post MSIs to an interrupt controller
via a mailbox accessed through the IOMMU. Suppose also that the IOMMU
generates MSIs itself in
On Thursday 01 May 2014 23:02:14 Cho KyongHo wrote:
- device can only do DMA to a limited address range
- DMA is noncoherent and needs manual cache management
- DMA address is at an offset from physical address
- some devices have an IOMMU
- some IOMMUs are shared between devices
-
On Thu, May 01, 2014 at 02:29:50PM +0100, Arnd Bergmann wrote:
On Thursday 01 May 2014 12:15:35 Dave Martin wrote:
On Tue, Apr 29, 2014 at 10:46:18PM +0200, Arnd Bergmann wrote:
On Tuesday 29 April 2014 19:16:02 Dave Martin wrote:
[...]
For example, suppose devices can post MSIs
On Thu, May 01, 2014 at 11:02:14PM +0900, Cho KyongHo wrote:
On Tue, 29 Apr 2014 23:00:29 +0200, Arnd Bergmann wrote:
On Tuesday 29 April 2014 13:07:54 Grant Grundler wrote:
On Tue, Apr 29, 2014 at 11:16 AM, Dave Martin dave.mar...@arm.com wrote:
...
An IOMMU is really a specialised
On 01/05/14 15:36, Dave Martin wrote:
On Thu, May 01, 2014 at 02:29:50PM +0100, Arnd Bergmann wrote:
On Thursday 01 May 2014 12:15:35 Dave Martin wrote:
On Tue, Apr 29, 2014 at 10:46:18PM +0200, Arnd Bergmann wrote:
On Tuesday 29 April 2014 19:16:02 Dave Martin wrote:
[...]
For example,
On Thursday 01 May 2014 15:36:54 Dave Martin wrote:
On Thu, May 01, 2014 at 02:29:50PM +0100, Arnd Bergmann wrote:
On Thursday 01 May 2014 12:15:35 Dave Martin wrote:
I'm not sure whether there is actually a SoC today that is MSI-capable
and contains an IOMMU, but all the components
On Thursday 01 May 2014 16:11:48 Marc Zyngier wrote:
On 01/05/14 15:36, Dave Martin wrote:
On Thu, May 01, 2014 at 02:29:50PM +0100, Arnd Bergmann wrote:
On Thursday 01 May 2014 12:15:35 Dave Martin wrote:
On Tue, Apr 29, 2014 at 10:46:18PM +0200, Arnd Bergmann wrote:
I don't understand.
On 01/05/14 16:53, Arnd Bergmann wrote:
On Thursday 01 May 2014 16:11:48 Marc Zyngier wrote:
On 01/05/14 15:36, Dave Martin wrote:
On Thu, May 01, 2014 at 02:29:50PM +0100, Arnd Bergmann wrote:
On Thursday 01 May 2014 12:15:35 Dave Martin wrote:
On Tue, Apr 29, 2014 at 10:46:18PM +0200, Arnd
On Thu, May 1, 2014 at 6:29 AM, Arnd Bergmann a...@arndb.de wrote:
...
GICv3 can descriminate between different MSI senders based on ID
signals on the bus.
Any idea what this is good for? Do we have to use it? It probably doesn't
fit very well into the way Linux handles MSIs today.
I can see
On 04/29/2014 03:00 PM, Arnd Bergmann wrote:
...
Yes. It's very complicated unfortunately, because we have to be
able to deal with arbitrary combinations of a lot of oddball cases
that can show up in random SoCs:
...
- a device may have DMA access to a bus that is invisible to the CPU
The
On Tue, Apr 29, 2014 at 11:00:29PM +0200, Arnd Bergmann wrote: On Tuesday 29
April 2014 13:07:54 Grant Grundler wrote: On Tue, Apr 29, 2014 at 11:16 AM,
Dave Martin dave.mar...@arm.com wrote:
...
An IOMMU is really a specialised bridge
Is a GART a bridge?
Depends what you mean by
On Mon, Apr 28, 2014 at 09:55:00PM +0200, Arnd Bergmann wrote:
On Monday 28 April 2014 20:30:56 Will Deacon wrote:
Hi Arnd,
[and thanks Thierry for CCing me -- I have been tangled up with this before
:)]
On Mon, Apr 28, 2014 at 01:05:30PM +0100, Arnd Bergmann wrote:
On Monday 28
Thierry Reding thierry.red...@gmail.com writes:
* PGP Signed by an unknown key
On Sun, Apr 27, 2014 at 08:23:06PM +0200, Arnd Bergmann wrote:
On Sunday 27 April 2014 13:07:43 Shaik Ameer Basha wrote:
+- mmu-masters: A phandle to device nodes representing the master for which
+
On Tue, Apr 29, 2014 at 11:16 AM, Dave Martin dave.mar...@arm.com wrote:
...
An IOMMU is really a specialised bridge
Is a GART a bridge?
IOMMUs can provide three basic functions:
1) remap address space to reach phys mem ranges that the device is
otherwise not capable of accessing (classic
On Tuesday 29 April 2014 19:16:02 Dave Martin wrote:
On Mon, Apr 28, 2014 at 09:55:00PM +0200, Arnd Bergmann wrote:
On Monday 28 April 2014 20:30:56 Will Deacon wrote:
device@4 {
compatible = some,ethernet;
iommus = /iommu@1;
};
On Tuesday 29 April 2014 13:07:54 Grant Grundler wrote:
On Tue, Apr 29, 2014 at 11:16 AM, Dave Martin dave.mar...@arm.com wrote:
...
An IOMMU is really a specialised bridge
Is a GART a bridge?
IOMMUs can provide three basic functions:
1) remap address space to reach phys mem ranges that
On Sun, Apr 27, 2014 at 08:23:06PM +0200, Arnd Bergmann wrote:
On Sunday 27 April 2014 13:07:43 Shaik Ameer Basha wrote:
+- mmu-masters: A phandle to device nodes representing the master for which
+ the System MMU can provide a translation. Any additional
values
+
On Monday 28 April 2014 12:39:20 Thierry Reding wrote:
On Sun, Apr 27, 2014 at 08:23:06PM +0200, Arnd Bergmann wrote:
On Sunday 27 April 2014 13:07:43 Shaik Ameer Basha wrote:
+- mmu-masters: A phandle to device nodes representing the master for
which
+ the System MMU
On Mon, Apr 28, 2014 at 12:56:03PM +0200, Arnd Bergmann wrote:
On Monday 28 April 2014 12:39:20 Thierry Reding wrote:
On Sun, Apr 27, 2014 at 08:23:06PM +0200, Arnd Bergmann wrote:
On Sunday 27 April 2014 13:07:43 Shaik Ameer Basha wrote:
+- mmu-masters: A phandle to device nodes
On Monday 28 April 2014 13:18:03 Thierry Reding wrote:
On Mon, Apr 28, 2014 at 12:56:03PM +0200, Arnd Bergmann wrote:
On Monday 28 April 2014 12:39:20 Thierry Reding wrote:
And possibly with a iommu-names property to go along with that. The idea
being that a device can be a master on
On Mon, Apr 28, 2014 at 02:05:30PM +0200, Arnd Bergmann wrote:
On Monday 28 April 2014 13:18:03 Thierry Reding wrote:
On Mon, Apr 28, 2014 at 12:56:03PM +0200, Arnd Bergmann wrote:
On Monday 28 April 2014 12:39:20 Thierry Reding wrote:
And possibly with a iommu-names property to go along
On 04/28/2014 05:18 AM, Thierry Reding wrote:
On Mon, Apr 28, 2014 at 12:56:03PM +0200, Arnd Bergmann wrote:
...
A lot of drivers probably only support one
master, so they can just set #iommu-cells=0, others might require
IDs that do not fit into one cell.
You mean #iommu-cells = 1 for
Hi Arnd,
[and thanks Thierry for CCing me -- I have been tangled up with this before
:)]
On Mon, Apr 28, 2014 at 01:05:30PM +0100, Arnd Bergmann wrote:
On Monday 28 April 2014 13:18:03 Thierry Reding wrote:
There still has to be one cell to specify which master. Unless perhaps
if they can
On Sunday 27 April 2014 13:07:43 Shaik Ameer Basha wrote:
+- mmu-masters: A phandle to device nodes representing the master for which
+ the System MMU can provide a translation. Any additional
values
+ after the phandle will be ignored because a System MMU never
+
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