On Thu, Sep 27, 2012 at 03:34:07PM -0600, Alex Williamson wrote:
It really seems like RMRRs are incompatible with IOMMU API use
though.
I don't think so. The concept of RMRR is just not defined well enough
(like the concept of unity mappings on the AMD side which is similar to
RMRR). The
On Thu, Sep 27, 2012 at 10:50:05PM +0100, David Woodhouse wrote:
That would include fairly much any USB host controller. The whole RMRR
concept is completely broken and should never have been invented. The
idea that firmware-controlled DMA should continue to happen *after* the
operating system
On Fri, 2012-09-28 at 11:46 +0200, Joerg Roedel wrote:
Even on modern hardware with modern (IOMMU aware) kernels there is still
this small time window when the OS has enabled the IOMMU and the USB
driver is not initialized yet. In this time window the RMRR memory
region is still necessary, no?
On Fri, Sep 28, 2012 at 11:23:23AM +0100, David Woodhouse wrote:
On Fri, 2012-09-28 at 11:46 +0200, Joerg Roedel wrote:
Even on modern hardware with modern (IOMMU aware) kernels there is still
this small time window when the OS has enabled the IOMMU and the USB
driver is not initialized
On Fri, Sep 28, 2012 at 06:40:08AM -0600, Alex Williamson wrote:
On Fri, 2012-09-28 at 11:43 +0200, Joerg Roedel wrote:
I don't think so. The concept of RMRR is just not defined well enough
(like the concept of unity mappings on the AMD side which is similar to
RMRR). The definition says,
On Fri, 2012-09-28 at 14:52 +0200, Joerg Roedel wrote:
On Fri, Sep 28, 2012 at 06:40:08AM -0600, Alex Williamson wrote:
On Fri, 2012-09-28 at 11:43 +0200, Joerg Roedel wrote:
I don't think so. The concept of RMRR is just not defined well enough
(like the concept of unity mappings on the
On Fri, Sep 28, 2012 at 12:36:05PM -0400, Linda Knippers wrote:
I can only speak to the HP servers. We have been shipping devices
'for a while' that provide sensor-type data to the platform. The
device does DMA writes to a range of memory (the RMRR) and
iLO does DMA reads of that data.
And
On Fri, Sep 28, 2012 at 07:01:06PM +0200, Joerg Roedel wrote:
On Fri, Sep 28, 2012 at 12:36:05PM -0400, Linda Knippers wrote:
I can only speak to the HP servers. We have been shipping devices
'for a while' that provide sensor-type data to the platform. The
device does DMA writes to a
On Fri, 2012-09-28 at 19:01 +0200, Joerg Roedel wrote:
On Fri, Sep 28, 2012 at 12:36:05PM -0400, Linda Knippers wrote:
I can only speak to the HP servers. We have been shipping devices
'for a while' that provide sensor-type data to the platform. The
device does DMA writes to a range of
On Fri, 2012-09-28 at 12:36 -0400, Linda Knippers wrote:
I can only speak to the HP servers. We have been shipping devices
'for a while' that provide sensor-type data to the platform. The
device does DMA writes to a range of memory (the RMRR) and
iLO does DMA reads of that data.
This
On Fri, 2012-09-28 at 20:15 +0100, David Woodhouse wrote:
On Fri, 2012-09-28 at 12:36 -0400, Linda Knippers wrote:
I can only speak to the HP servers. We have been shipping devices
'for a while' that provide sensor-type data to the platform. The
device does DMA writes to a range of memory
[adding David Woodhouse]
On Tue, 2012-09-18 at 16:49 +, Tom Mingarelli wrote:
When a 32bit PCI device is removed from the SI Domain, the RMRR information
for this device becomes invalid and needs to be reprocessed to avoid DMA
Read errors. These errors are evidenced by the Present bit
To: Mingarelli, Thomas
Cc: iommu@lists.linux-foundation.org; Knippers, Linda; Khan, Shuah; Don Dutile;
David Woodhouse
Subject: Re: [PATCH v2] Intel IOMMU patch to reprocess RMRR info
[adding David Woodhouse]
On Tue, 2012-09-18 at 16:49 +, Tom Mingarelli wrote:
When a 32bit PCI device is removed
On Thu, 2012-09-27 at 15:34 -0600, Alex Williamson wrote:
It really seems like RMRRs are incompatible with IOMMU API use though.
If an RMRR is setup for a VM domain, that's bad because a) it gives the
VM direct access to that range of host memory, and b) it interferes with
the guest use of the
; David Woodhouse
Subject: Re: [PATCH v2] Intel IOMMU patch to reprocess RMRR info
[adding David Woodhouse]
On Tue, 2012-09-18 at 16:49 +, Tom Mingarelli wrote:
When a 32bit PCI device is removed from the SI Domain, the RMRR information
for this device becomes invalid and needs
: [PATCH v2] Intel IOMMU patch to reprocess RMRR info
[adding David Woodhouse]
On Tue, 2012-09-18 at 16:49 +, Tom Mingarelli wrote:
When a 32bit PCI device is removed from the SI Domain, the RMRR information
for this device becomes invalid and needs to be reprocessed to avoid DMA
Read errors
When a 32bit PCI device is removed from the SI Domain, the RMRR information
for this device becomes invalid and needs to be reprocessed to avoid DMA
Read errors. These errors are evidenced by the Present bit being cleared in
the device's context entry. Fixing this problem with an enhancement to
When a 32bit PCI device is removed from the SI Domain, the RMRR information
for this device becomes invalid and needs to be reprocessed to avoid DMA
Read errors. These errors are evidenced by the Present bit being cleared in
the device's context entry. Fixing this problem with an enhancement to
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