Re: [PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU
On Tue, Oct 06, 2020 at 12:26:45PM +0800, Yong Wu wrote: > Hi Krzysztof, > > On Fri, 2020-10-02 at 13:10 +0200, Krzysztof Kozlowski wrote: > > On Wed, Sep 30, 2020 at 03:06:29PM +0800, Yong Wu wrote: > > > This patch adds decriptions for mt8192 IOMMU and SMI. > > > > > > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation > > > table format. The M4U-SMI HW diagram is as below: > > > > > > EMI > > >| > > > M4U > > >| > > > > > >SMI Common > > > > > >| > > > +---+--+--+--+---+ > > > | | | | .. | | > > > | | | | | | > > > larb0 larb1 larb2 larb4 .. larb19 larb20 > > > disp0 disp1 mdpvdec IPE IPE > > > > > > All the connections are HW fixed, SW can NOT adjust it. > > > > > > mt8192 M4U support 0~16GB iova range. we preassign different engines > > > into different iova ranges: > > > > > > domain-id module iova-range larbs > > >0 disp0 ~ 4G larb0/1 > > >1 vcodec 4G ~ 8G larb4/5/7 > > >2 cam/mdp 8G ~ 12G > > > larb2/9/11/13/14/16/17/18/19/20 > > >3 CCU00x4000_ ~ 0x43ff_ larb13: port 9/10 > > >4 CCU10x4400_ ~ 0x47ff_ larb14: port 4/5 > > > > > > The iova range for CCU0/1(camera control unit) is HW requirement. > > > > > > Signed-off-by: Yong Wu > > > Reviewed-by: Rob Herring > > > --- > > > .../bindings/iommu/mediatek,iommu.yaml| 9 +- > > > .../mediatek,smi-common.yaml | 5 +- > > > .../memory-controllers/mediatek,smi-larb.yaml | 3 +- > > > include/dt-bindings/memory/mt8192-larb-port.h | 239 ++ > > > 4 files changed, 251 insertions(+), 5 deletions(-) > > > create mode 100644 include/dt-bindings/memory/mt8192-larb-port.h > > > > I see it depends on previous patches but does it have to be within one > > commit? Is it not bisectable? The memory changes/bindings could go via > > memory tree if this is split. > > Thanks for the view. > > I can split this into two patchset in next version, one is for iommu and > the other is for smi. > > Only the patch [18/24] change both the code(iommu and smi). I don't plan > to split it, and the smi patch[24/24] don't depend on it(won't > conflict). It got too late in the cycle, so I am not going to take the 24/24 now. > > since 18/24 also touch the smi code, I expect it could get Acked-by from > you or Matthias, then Joerg could take it. Sure. I acked it. Best regards, Krzysztof ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU
Hi Krzysztof, On Fri, 2020-10-02 at 13:10 +0200, Krzysztof Kozlowski wrote: > On Wed, Sep 30, 2020 at 03:06:29PM +0800, Yong Wu wrote: > > This patch adds decriptions for mt8192 IOMMU and SMI. > > > > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation > > table format. The M4U-SMI HW diagram is as below: > > > > EMI > >| > > M4U > >| > > > >SMI Common > > > >| > > +---+--+--+--+---+ > > | | | | .. | | > > | | | | | | > > larb0 larb1 larb2 larb4 .. larb19 larb20 > > disp0 disp1 mdpvdec IPE IPE > > > > All the connections are HW fixed, SW can NOT adjust it. > > > > mt8192 M4U support 0~16GB iova range. we preassign different engines > > into different iova ranges: > > > > domain-id module iova-range larbs > >0 disp0 ~ 4G larb0/1 > >1 vcodec 4G ~ 8G larb4/5/7 > >2 cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20 > >3 CCU00x4000_ ~ 0x43ff_ larb13: port 9/10 > >4 CCU10x4400_ ~ 0x47ff_ larb14: port 4/5 > > > > The iova range for CCU0/1(camera control unit) is HW requirement. > > > > Signed-off-by: Yong Wu > > Reviewed-by: Rob Herring > > --- > > .../bindings/iommu/mediatek,iommu.yaml| 9 +- > > .../mediatek,smi-common.yaml | 5 +- > > .../memory-controllers/mediatek,smi-larb.yaml | 3 +- > > include/dt-bindings/memory/mt8192-larb-port.h | 239 ++ > > 4 files changed, 251 insertions(+), 5 deletions(-) > > create mode 100644 include/dt-bindings/memory/mt8192-larb-port.h > > I see it depends on previous patches but does it have to be within one > commit? Is it not bisectable? The memory changes/bindings could go via > memory tree if this is split. Thanks for the view. I can split this into two patchset in next version, one is for iommu and the other is for smi. Only the patch [18/24] change both the code(iommu and smi). I don't plan to split it, and the smi patch[24/24] don't depend on it(won't conflict). since 18/24 also touch the smi code, I expect it could get Acked-by from you or Matthias, then Joerg could take it. Thanks. > > Best regards, > Krzysztof ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU
On Wed, Sep 30, 2020 at 03:06:29PM +0800, Yong Wu wrote: > This patch adds decriptions for mt8192 IOMMU and SMI. > > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation > table format. The M4U-SMI HW diagram is as below: > > EMI >| > M4U >| > >SMI Common > >| > +---+--+--+--+---+ > | | | | .. | | > | | | | | | > larb0 larb1 larb2 larb4 .. larb19 larb20 > disp0 disp1 mdpvdec IPE IPE > > All the connections are HW fixed, SW can NOT adjust it. > > mt8192 M4U support 0~16GB iova range. we preassign different engines > into different iova ranges: > > domain-id module iova-range larbs >0 disp0 ~ 4G larb0/1 >1 vcodec 4G ~ 8G larb4/5/7 >2 cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20 >3 CCU00x4000_ ~ 0x43ff_ larb13: port 9/10 >4 CCU10x4400_ ~ 0x47ff_ larb14: port 4/5 > > The iova range for CCU0/1(camera control unit) is HW requirement. > > Signed-off-by: Yong Wu > Reviewed-by: Rob Herring > --- > .../bindings/iommu/mediatek,iommu.yaml| 9 +- > .../mediatek,smi-common.yaml | 5 +- > .../memory-controllers/mediatek,smi-larb.yaml | 3 +- > include/dt-bindings/memory/mt8192-larb-port.h | 239 ++ > 4 files changed, 251 insertions(+), 5 deletions(-) > create mode 100644 include/dt-bindings/memory/mt8192-larb-port.h I see it depends on previous patches but does it have to be within one commit? Is it not bisectable? The memory changes/bindings could go via memory tree if this is split. Best regards, Krzysztof ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
[PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU
This patch adds decriptions for mt8192 IOMMU and SMI. mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation table format. The M4U-SMI HW diagram is as below: EMI | M4U | SMI Common | +---+--+--+--+---+ | | | | .. | | | | | | | | larb0 larb1 larb2 larb4 .. larb19 larb20 disp0 disp1 mdpvdec IPE IPE All the connections are HW fixed, SW can NOT adjust it. mt8192 M4U support 0~16GB iova range. we preassign different engines into different iova ranges: domain-id module iova-range larbs 0 disp0 ~ 4G larb0/1 1 vcodec 4G ~ 8G larb4/5/7 2 cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20 3 CCU00x4000_ ~ 0x43ff_ larb13: port 9/10 4 CCU10x4400_ ~ 0x47ff_ larb14: port 4/5 The iova range for CCU0/1(camera control unit) is HW requirement. Signed-off-by: Yong Wu Reviewed-by: Rob Herring --- .../bindings/iommu/mediatek,iommu.yaml| 9 +- .../mediatek,smi-common.yaml | 5 +- .../memory-controllers/mediatek,smi-larb.yaml | 3 +- include/dt-bindings/memory/mt8192-larb-port.h | 239 ++ 4 files changed, 251 insertions(+), 5 deletions(-) create mode 100644 include/dt-bindings/memory/mt8192-larb-port.h diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index eae773ad53a3..a7f41cdf3aca 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -75,6 +75,7 @@ properties: - mediatek,mt6779-m4u # mt6779 generation two HW - mediatek,mt8173-m4u # mt8173 generation two HW - mediatek,mt8183-m4u # mt8183 generation two HW + - mediatek,mt8192-m4u # mt8192 generation two HW - description: mt7623 generation one HW items: @@ -90,7 +91,7 @@ properties: clocks: description: | bclk is optional. here is the list which require this bclk: - mt2701, mt2712, mt7623 and mt8173. + mt2701, mt2712, mt7623, mt8173 and mt8192. M4U will use the EMI clock which always has been enabled before kernel if there is no this bclk. items: @@ -116,7 +117,11 @@ properties: dt-binding/memory/mt2712-larb-port.h for mt2712, dt-binding/memory/mt6779-larb-port.h for mt6779, dt-binding/memory/mt8173-larb-port.h for mt8173, - dt-binding/memory/mt8183-larb-port.h for mt8183. + dt-binding/memory/mt8183-larb-port.h for mt8183, + dt-binding/memory/mt8192-larb-port.h for mt8192. + + power-domains: +maxItems: 1 required: - compatible diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml index 76ecc7205438..d3cb4d853e71 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml @@ -15,7 +15,7 @@ description: |+ MediaTek SMI have two generations of HW architecture, here is the list which generation the SoCs use: generation 1: mt2701 and mt7623. - generation 2: mt2712, mt6779, mt8173 and mt8183. + generation 2: mt2712, mt6779, mt8173, mt8183 and mt8192. There's slight differences between the two SMI, for generation 2, the register which control the iommu port is at each larb's register base. But @@ -33,6 +33,7 @@ properties: - mediatek,mt6779-smi-common - mediatek,mt8173-smi-common - mediatek,mt8183-smi-common + - mediatek,mt8192-smi-common - description: for mt7623 items: @@ -46,7 +47,7 @@ properties: description: | apb and smi are mandatory. the async is only for generation 1 smi HW. gals(global async local sync) also is optional, here is the list which - require gals: mt6779 and mt8183. + require gals: mt6779, mt8183 and mt8192. minItems: 2 maxItems: 4 items: diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml index ea418113bf27..f5ba43638c37 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml @@ -21,6 +21,7 @@ properties: -
