> On Jun 15, 2021, at 12:20 PM, Robin Murphy wrote:
>
> On 2021-06-15 19:14, Nadav Amit wrote:
>>> On Jun 15, 2021, at 5:55 AM, Robin Murphy wrote:
>>>
>>> On 2021-06-07 19:25, Nadav Amit wrote:
From: Nadav Amit
AMD's IOMMU can flush efficiently (i.e., in a single flush) any
On 2021-06-15 19:14, Nadav Amit wrote:
On Jun 15, 2021, at 5:55 AM, Robin Murphy wrote:
On 2021-06-07 19:25, Nadav Amit wrote:
From: Nadav Amit
AMD's IOMMU can flush efficiently (i.e., in a single flush) any range.
This is in contrast, for instnace, to Intel IOMMUs that have a limit on
> On Jun 15, 2021, at 5:55 AM, Robin Murphy wrote:
>
> On 2021-06-07 19:25, Nadav Amit wrote:
>> From: Nadav Amit
>> AMD's IOMMU can flush efficiently (i.e., in a single flush) any range.
>> This is in contrast, for instnace, to Intel IOMMUs that have a limit on
>> the number of pages that
On 2021-06-07 19:25, Nadav Amit wrote:
From: Nadav Amit
AMD's IOMMU can flush efficiently (i.e., in a single flush) any range.
This is in contrast, for instnace, to Intel IOMMUs that have a limit on
the number of pages that can be flushed in a single flush. In addition,
AMD's IOMMU do not
From: Nadav Amit
AMD's IOMMU can flush efficiently (i.e., in a single flush) any range.
This is in contrast, for instnace, to Intel IOMMUs that have a limit on
the number of pages that can be flushed in a single flush. In addition,
AMD's IOMMU do not care about the page-size, so changes of the
