Re: [PATCH v4 1/3] dt-bindings: memory: mediatek: Convert SMI to DT

2020-11-01 Thread Krzysztof Kozlowski
On Mon, 2 Nov 2020 at 06:31, Yong Wu  wrote:
>
> On Sat, 2020-10-31 at 12:36 +0100, Krzysztof Kozlowski wrote:
> > On Fri, Oct 30, 2020 at 05:12:52PM +0800, Yong Wu wrote:
> > > Convert MediaTek SMI to DT schema.
> > >
> > > CC: Fabien Parent 
> > > CC: Ming-Fan Chen 
> > > CC: Matthias Brugger 
> > > Signed-off-by: Yong Wu 
> > > ---
> > >  .../mediatek,smi-common.txt   |  50 ---
> > >  .../mediatek,smi-common.yaml  | 140 ++
> > >  .../memory-controllers/mediatek,smi-larb.txt  |  50 ---
> > >  .../memory-controllers/mediatek,smi-larb.yaml | 129 
> > >  4 files changed, 269 insertions(+), 100 deletions(-)
> > >  delete mode 100644 
> > > Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> >
> > +Cc Honghui Zhang,
>
> As comment [1], Honghui's address is not valid now. I will act for him.
>
> >
> > Your Ack is needed as you contributed descriptions to the bindings and
> > work is being relicensed to GPL-2.0-only OR BSD-2-Clause.
>
> "GPL-2.0-only OR BSD-2-Clause" is required when we run check-patch.
>
> If I still use "GPL-2.0-only", then the contributors' Ack/SoB is not
> needed, right?

That would be one solution but I was thinking to proceed with only
your agreement. You were the main contributor to these files. Honghui
added a few descriptions. Other developers added only compatibles.
Since we cannot reach Honghui, I would assume that your agreement
(Sign-off) is enough.

Best regards,
Krzysztof
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Re: [PATCH v4 1/3] dt-bindings: memory: mediatek: Convert SMI to DT

2020-11-01 Thread Yong Wu
On Sat, 2020-10-31 at 12:36 +0100, Krzysztof Kozlowski wrote:
> On Fri, Oct 30, 2020 at 05:12:52PM +0800, Yong Wu wrote:
> > Convert MediaTek SMI to DT schema.
> > 
> > CC: Fabien Parent 
> > CC: Ming-Fan Chen 
> > CC: Matthias Brugger 
> > Signed-off-by: Yong Wu 
> > ---
> >  .../mediatek,smi-common.txt   |  50 ---
> >  .../mediatek,smi-common.yaml  | 140 ++
> >  .../memory-controllers/mediatek,smi-larb.txt  |  50 ---
> >  .../memory-controllers/mediatek,smi-larb.yaml | 129 
> >  4 files changed, 269 insertions(+), 100 deletions(-)
> >  delete mode 100644 
> > Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> 
> +Cc Honghui Zhang,

As comment [1], Honghui's address is not valid now. I will act for him.

> 
> Your Ack is needed as you contributed descriptions to the bindings and
> work is being relicensed to GPL-2.0-only OR BSD-2-Clause.

"GPL-2.0-only OR BSD-2-Clause" is required when we run check-patch.

If I still use "GPL-2.0-only", then the contributors' Ack/SoB is not
needed, right?

[1]
https://lore.kernel.org/linux-iommu/1604051256.26323.100.camel@mhfsdcap03/T/#u

> 
> 
> Best regards,
> Krzysztof
> 
> 
> 
> 
> >  create mode 100644 
> > Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> >  delete mode 100644 
> > Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
> >  create mode 100644 
> > Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
> > 
> > diff --git 
> > a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> >  
> > b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> > deleted file mode 100644
> > index dbafffe3f41e..
> > --- 
> > a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> > +++ /dev/null
> > @@ -1,50 +0,0 @@
> > -SMI (Smart Multimedia Interface) Common
> > -
> > -The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
> > -
> > -Mediatek SMI have two generations of HW architecture, here is the list
> > -which generation the SoCs use:
> > -generation 1: mt2701 and mt7623.
> > -generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183.
> > -
> > -There's slight differences between the two SMI, for generation 2, the
> > -register which control the iommu port is at each larb's register base. But
> > -for generation 1, the register is at smi ao base(smi always on register
> > -base). Besides that, the smi async clock should be prepared and enabled for
> > -SMI generation 1 to transform the smi clock into emi clock domain, but 
> > that is
> > -not needed for SMI generation 2.
> > -
> > -Required properties:
> > -- compatible : must be one of :
> > -   "mediatek,mt2701-smi-common"
> > -   "mediatek,mt2712-smi-common"
> > -   "mediatek,mt6779-smi-common"
> > -   "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
> > -   "mediatek,mt8167-smi-common"
> > -   "mediatek,mt8173-smi-common"
> > -   "mediatek,mt8183-smi-common"
> > -- reg : the register and size of the SMI block.
> > -- power-domains : a phandle to the power domain of this local arbiter.
> > -- clocks : Must contain an entry for each entry in clock-names.
> > -- clock-names : must contain 3 entries for generation 1 smi HW and 2 
> > entries
> > -  for generation 2 smi HW as follows:
> > -  - "apb" : Advanced Peripheral Bus clock, It's the clock for setting
> > -   the register.
> > -  - "smi" : It's the clock for transfer data and command.
> > -   They may be the same if both source clocks are the same.
> > -  - "async" : asynchronous clock, it help transform the smi clock into the 
> > emi
> > - clock domain, this clock is only needed by generation 1 smi HW.
> > -  and these 2 option clocks for generation 2 smi HW:
> > -  - "gals0": the path0 clock of GALS(Global Async Local Sync).
> > -  - "gals1": the path1 clock of GALS(Global Async Local Sync).
> > -  Here is the list which has this GALS: mt6779 and mt8183.
> > -
> > -Example:
> > -   smi_common: smi@14022000 {
> > -   compatible = "mediatek,mt8173-smi-common";
> > -   reg = <0 0x14022000 0 0x1000>;
> > -   power-domains = < MT8173_POWER_DOMAIN_MM>;
> > -   clocks = < CLK_MM_SMI_COMMON>,
> > -< CLK_MM_SMI_COMMON>;
> > -   clock-names = "apb", "smi";
> > -   };
> > diff --git 
> > a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> >  
> > b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> > new file mode 100644
> > index ..e050a0c2aed6
> > --- /dev/null
> > +++ 
> > b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> > @@ -0,0 +1,140 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright (c) 2020 MediaTek Inc.
> > +%YAML 1.2
> > +---
> > +$id: 
> > 

Re: [PATCH v4 1/3] dt-bindings: memory: mediatek: Convert SMI to DT schema

2020-10-31 Thread Krzysztof Kozlowski
On Fri, Oct 30, 2020 at 05:12:52PM +0800, Yong Wu wrote:
> Convert MediaTek SMI to DT schema.
> 
> CC: Fabien Parent 
> CC: Ming-Fan Chen 
> CC: Matthias Brugger 
> Signed-off-by: Yong Wu 
> ---
>  .../mediatek,smi-common.txt   |  50 ---
>  .../mediatek,smi-common.yaml  | 140 ++
>  .../memory-controllers/mediatek,smi-larb.txt  |  50 ---
>  .../memory-controllers/mediatek,smi-larb.yaml | 129 
>  4 files changed, 269 insertions(+), 100 deletions(-)
>  delete mode 100644 
> Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt

+Cc Honghui Zhang,

Your Ack is needed as you contributed descriptions to the bindings and
work is being relicensed to GPL-2.0-only OR BSD-2-Clause.


Best regards,
Krzysztof




>  create mode 100644 
> Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
>  delete mode 100644 
> Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
>  create mode 100644 
> Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
> 
> diff --git 
> a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
>  
> b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> deleted file mode 100644
> index dbafffe3f41e..
> --- 
> a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> +++ /dev/null
> @@ -1,50 +0,0 @@
> -SMI (Smart Multimedia Interface) Common
> -
> -The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
> -
> -Mediatek SMI have two generations of HW architecture, here is the list
> -which generation the SoCs use:
> -generation 1: mt2701 and mt7623.
> -generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183.
> -
> -There's slight differences between the two SMI, for generation 2, the
> -register which control the iommu port is at each larb's register base. But
> -for generation 1, the register is at smi ao base(smi always on register
> -base). Besides that, the smi async clock should be prepared and enabled for
> -SMI generation 1 to transform the smi clock into emi clock domain, but that 
> is
> -not needed for SMI generation 2.
> -
> -Required properties:
> -- compatible : must be one of :
> - "mediatek,mt2701-smi-common"
> - "mediatek,mt2712-smi-common"
> - "mediatek,mt6779-smi-common"
> - "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
> - "mediatek,mt8167-smi-common"
> - "mediatek,mt8173-smi-common"
> - "mediatek,mt8183-smi-common"
> -- reg : the register and size of the SMI block.
> -- power-domains : a phandle to the power domain of this local arbiter.
> -- clocks : Must contain an entry for each entry in clock-names.
> -- clock-names : must contain 3 entries for generation 1 smi HW and 2 entries
> -  for generation 2 smi HW as follows:
> -  - "apb" : Advanced Peripheral Bus clock, It's the clock for setting
> - the register.
> -  - "smi" : It's the clock for transfer data and command.
> - They may be the same if both source clocks are the same.
> -  - "async" : asynchronous clock, it help transform the smi clock into the 
> emi
> -   clock domain, this clock is only needed by generation 1 smi HW.
> -  and these 2 option clocks for generation 2 smi HW:
> -  - "gals0": the path0 clock of GALS(Global Async Local Sync).
> -  - "gals1": the path1 clock of GALS(Global Async Local Sync).
> -  Here is the list which has this GALS: mt6779 and mt8183.
> -
> -Example:
> - smi_common: smi@14022000 {
> - compatible = "mediatek,mt8173-smi-common";
> - reg = <0 0x14022000 0 0x1000>;
> - power-domains = < MT8173_POWER_DOMAIN_MM>;
> - clocks = < CLK_MM_SMI_COMMON>,
> -  < CLK_MM_SMI_COMMON>;
> - clock-names = "apb", "smi";
> - };
> diff --git 
> a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
>  
> b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> new file mode 100644
> index ..e050a0c2aed6
> --- /dev/null
> +++ 
> b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> @@ -0,0 +1,140 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2020 MediaTek Inc.
> +%YAML 1.2
> +---
> +$id: 
> http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SMI (Smart Multimedia Interface) Common
> +
> +maintainers:
> +  - Yong Wu 
> +
> +description: |+
> +  The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
> +
> +  MediaTek SMI have two generations of HW architecture, here is the list
> +  which generation the SoCs use:
> +  generation 1: mt2701 and mt7623.
> +  generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183.
> +
> +  There's slight differences between the 

Re: [PATCH v4 1/3] dt-bindings: memory: mediatek: Convert SMI to DT schema

2020-10-30 Thread Rob Herring
On Fri, 30 Oct 2020 17:12:52 +0800, Yong Wu wrote:
> Convert MediaTek SMI to DT schema.
> 
> CC: Fabien Parent 
> CC: Ming-Fan Chen 
> CC: Matthias Brugger 
> Signed-off-by: Yong Wu 
> ---
>  .../mediatek,smi-common.txt   |  50 ---
>  .../mediatek,smi-common.yaml  | 140 ++
>  .../memory-controllers/mediatek,smi-larb.txt  |  50 ---
>  .../memory-controllers/mediatek,smi-larb.yaml | 129 
>  4 files changed, 269 insertions(+), 100 deletions(-)
>  delete mode 100644 
> Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
>  create mode 100644 
> Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
>  delete mode 100644 
> Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
>  create mode 100644 
> Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
> 


My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:
./Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml:84:8:
 [warning] wrong indentation: expected 6 but found 7 (indentation)
./Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml:98:13:
 [warning] wrong indentation: expected 10 but found 12 (indentation)
./Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml:41:8:
 [warning] wrong indentation: expected 6 but found 7 (indentation)

dtschema/dtc warnings/errors:


See https://patchwork.ozlabs.org/patch/1390887

The base for the patch is generally the last rc1. Any dependencies
should be noted.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

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[PATCH v4 1/3] dt-bindings: memory: mediatek: Convert SMI to DT schema

2020-10-30 Thread Yong Wu
Convert MediaTek SMI to DT schema.

CC: Fabien Parent 
CC: Ming-Fan Chen 
CC: Matthias Brugger 
Signed-off-by: Yong Wu 
---
 .../mediatek,smi-common.txt   |  50 ---
 .../mediatek,smi-common.yaml  | 140 ++
 .../memory-controllers/mediatek,smi-larb.txt  |  50 ---
 .../memory-controllers/mediatek,smi-larb.yaml | 129 
 4 files changed, 269 insertions(+), 100 deletions(-)
 delete mode 100644 
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
 create mode 100644 
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
 delete mode 100644 
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
 create mode 100644 
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml

diff --git 
a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt 
b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
deleted file mode 100644
index dbafffe3f41e..
--- 
a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-SMI (Smart Multimedia Interface) Common
-
-The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
-
-Mediatek SMI have two generations of HW architecture, here is the list
-which generation the SoCs use:
-generation 1: mt2701 and mt7623.
-generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183.
-
-There's slight differences between the two SMI, for generation 2, the
-register which control the iommu port is at each larb's register base. But
-for generation 1, the register is at smi ao base(smi always on register
-base). Besides that, the smi async clock should be prepared and enabled for
-SMI generation 1 to transform the smi clock into emi clock domain, but that is
-not needed for SMI generation 2.
-
-Required properties:
-- compatible : must be one of :
-   "mediatek,mt2701-smi-common"
-   "mediatek,mt2712-smi-common"
-   "mediatek,mt6779-smi-common"
-   "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
-   "mediatek,mt8167-smi-common"
-   "mediatek,mt8173-smi-common"
-   "mediatek,mt8183-smi-common"
-- reg : the register and size of the SMI block.
-- power-domains : a phandle to the power domain of this local arbiter.
-- clocks : Must contain an entry for each entry in clock-names.
-- clock-names : must contain 3 entries for generation 1 smi HW and 2 entries
-  for generation 2 smi HW as follows:
-  - "apb" : Advanced Peripheral Bus clock, It's the clock for setting
-   the register.
-  - "smi" : It's the clock for transfer data and command.
-   They may be the same if both source clocks are the same.
-  - "async" : asynchronous clock, it help transform the smi clock into the emi
- clock domain, this clock is only needed by generation 1 smi HW.
-  and these 2 option clocks for generation 2 smi HW:
-  - "gals0": the path0 clock of GALS(Global Async Local Sync).
-  - "gals1": the path1 clock of GALS(Global Async Local Sync).
-  Here is the list which has this GALS: mt6779 and mt8183.
-
-Example:
-   smi_common: smi@14022000 {
-   compatible = "mediatek,mt8173-smi-common";
-   reg = <0 0x14022000 0 0x1000>;
-   power-domains = < MT8173_POWER_DOMAIN_MM>;
-   clocks = < CLK_MM_SMI_COMMON>,
-< CLK_MM_SMI_COMMON>;
-   clock-names = "apb", "smi";
-   };
diff --git 
a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml 
b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
new file mode 100644
index ..e050a0c2aed6
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
@@ -0,0 +1,140 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SMI (Smart Multimedia Interface) Common
+
+maintainers:
+  - Yong Wu 
+
+description: |+
+  The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
+
+  MediaTek SMI have two generations of HW architecture, here is the list
+  which generation the SoCs use:
+  generation 1: mt2701 and mt7623.
+  generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183.
+
+  There's slight differences between the two SMI, for generation 2, the
+  register which control the iommu port is at each larb's register base. But
+  for generation 1, the register is at smi ao base(smi always on register
+  base). Besides that, the smi async clock should be prepared and enabled for
+  SMI generation 1 to transform the smi clock into emi clock domain, but that 
is
+  not needed for SMI generation 2.
+
+properties:
+  compatible:
+oneOf:
+  - enum: