Re: [PATCH v6 04/10] iommu/mediatek: Setting MISC_CTRL register

On 03/07/2020 06:41, Chao Hao wrote: > Add F_MMU_IN_ORDER_WR_EN_MASK and F_MMU_STANDARD_AXI_MODE_EN_MASK > definitions in MISC_CTRL register. > F_MMU_STANDARD_AXI_MODE_EN_MASK: > If we set F_MMU_STANDARD_AXI_MODE_EN_MASK (bit[3][19] = 0, not follow > standard AXI protocol), the iommu will priori

[PATCH v6 04/10] iommu/mediatek: Setting MISC_CTRL register

Add F_MMU_IN_ORDER_WR_EN_MASK and F_MMU_STANDARD_AXI_MODE_EN_MASK definitions in MISC_CTRL register. F_MMU_STANDARD_AXI_MODE_EN_MASK: If we set F_MMU_STANDARD_AXI_MODE_EN_MASK (bit[3][19] = 0, not follow standard AXI protocol), the iommu will priorize sending of urgent read command over a normal re