Re: [PATCH v7 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

2017-06-13 Thread Lorenzo Pieralisi
Hi Rafael, Lv, On Thu, Jun 08, 2017 at 07:13:24PM +0200, Rafael J. Wysocki wrote: > On Thu, Jun 8, 2017 at 6:32 PM, Lorenzo Pieralisi > wrote: > > On Tue, May 30, 2017 at 05:33:38PM +0530, Geetha sowjanya wrote: > >> Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. > >> 1. Errata I

Re: [PATCH v7 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

2017-06-08 Thread Robin Murphy
On 08/06/17 18:13, Rafael J. Wysocki wrote: > On Thu, Jun 8, 2017 at 6:32 PM, Lorenzo Pieralisi > wrote: >> On Tue, May 30, 2017 at 05:33:38PM +0530, Geetha sowjanya wrote: >>> Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. >>> 1. Errata ID #74 >>>SMMU register alias Page 1 is

Re: [PATCH v7 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

2017-06-08 Thread Rafael J. Wysocki
On Thu, Jun 8, 2017 at 6:32 PM, Lorenzo Pieralisi wrote: > On Tue, May 30, 2017 at 05:33:38PM +0530, Geetha sowjanya wrote: >> Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. >> 1. Errata ID #74 >>SMMU register alias Page 1 is not implemented >> 2. Errata ID #126 >>SMMU doe

Re: [PATCH v7 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

2017-06-08 Thread Lorenzo Pieralisi
On Tue, May 30, 2017 at 05:33:38PM +0530, Geetha sowjanya wrote: > Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. > 1. Errata ID #74 >SMMU register alias Page 1 is not implemented > 2. Errata ID #126 >SMMU doesnt support unique IRQ lines and also MSI for gerror, >eventq

Re: [PATCH v7 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

2017-05-30 Thread Robert Richter
On 30.05.17 17:33:38, Geetha sowjanya wrote: > Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. > 1. Errata ID #74 >SMMU register alias Page 1 is not implemented > 2. Errata ID #126 >SMMU doesnt support unique IRQ lines and also MSI for gerror, >eventq and cmdq-sync > >

[PATCH v7 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

2017-05-30 Thread Geetha sowjanya
Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. 1. Errata ID #74 SMMU register alias Page 1 is not implemented 2. Errata ID #126 SMMU doesnt support unique IRQ lines and also MSI for gerror, eventq and cmdq-sync The following patchset does software workaround for these two