Re: [PATCH v7 1/3] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model
On Tue, Jun 20, 2017 at 10:51:23AM +0200, Robert Richter wrote: > On 20.06.17 10:19:43, Robert Richter wrote: > > On 30.05.17 17:33:39, Geetha sowjanya wrote: > > > From: Linu Cherian > > > > + /* > > > + * Override the size, for Cavium ThunderX2 implementation > > > + * which doesn't support the page 1 SMMU register space. > > > + */ > > > + if (smmu->model == ACPI_IORT_SMMU_CAVIUM_CN99XX) > > > > Geetha, > > > > please resubmit the series since the macro changed to > > ACPI_IORT_SMMU_V3_CAVIUM_CN99XX: > > > > > > https://github.com/acpica/acpica/commit/d00a4eb86e64bb4fa70f57ab5e5ca0a4ca2ad8ef#diff-a572aac2ccc26fe4a901616d7fdba859R1053 > > Rafael, Bob, > > btw, I haven't seen > > https://github.com/acpica/acpica/commit/d00a4eb86e64 > > yet in linux-pm:linux-next. We would like to see this in 4.13 also. Is > it on the way already? Yes it would be great to understand how we can make sure IORT and related ACPICA changes can be kept in sync for this merge window, it is -rc6 already so it is getting a bit late in the cycle. Thanks, Lorenzo ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH v7 1/3] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model
On 20.06.17 10:19:43, Robert Richter wrote: > On 30.05.17 17:33:39, Geetha sowjanya wrote: > > From: Linu Cherian > > + /* > > +* Override the size, for Cavium ThunderX2 implementation > > +* which doesn't support the page 1 SMMU register space. > > +*/ > > + if (smmu->model == ACPI_IORT_SMMU_CAVIUM_CN99XX) > > Geetha, > > please resubmit the series since the macro changed to > ACPI_IORT_SMMU_V3_CAVIUM_CN99XX: > > > https://github.com/acpica/acpica/commit/d00a4eb86e64bb4fa70f57ab5e5ca0a4ca2ad8ef#diff-a572aac2ccc26fe4a901616d7fdba859R1053 Rafael, Bob, btw, I haven't seen https://github.com/acpica/acpica/commit/d00a4eb86e64 yet in linux-pm:linux-next. We would like to see this in 4.13 also. Is it on the way already? Thanks, -Robert ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH v7 1/3] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model
On 30.05.17 17:33:39, Geetha sowjanya wrote:
> From: Linu Cherian
>
> Cavium ThunderX2 implementation doesn't support second page in SMMU
> register space. Hence, resource size is set as 64k for this model.
>
> Signed-off-by: Linu Cherian
> Signed-off-by: Geetha Sowjanya
> ---
> drivers/acpi/arm64/iort.c | 10 +-
> 1 files changed, 9 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
> index c5fecf9..bba2b59 100644
> --- a/drivers/acpi/arm64/iort.c
> +++ b/drivers/acpi/arm64/iort.c
> @@ -833,12 +833,20 @@ static void __init arm_smmu_v3_init_resources(struct
> resource *res,
> {
> struct acpi_iort_smmu_v3 *smmu;
> int num_res = 0;
> + unsigned long size = SZ_128K;
>
> /* Retrieve SMMUv3 specific data */
> smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
>
> + /*
> + * Override the size, for Cavium ThunderX2 implementation
> + * which doesn't support the page 1 SMMU register space.
> + */
> + if (smmu->model == ACPI_IORT_SMMU_CAVIUM_CN99XX)
Geetha,
please resubmit the series since the macro changed to
ACPI_IORT_SMMU_V3_CAVIUM_CN99XX:
https://github.com/acpica/acpica/commit/d00a4eb86e64bb4fa70f57ab5e5ca0a4ca2ad8ef#diff-a572aac2ccc26fe4a901616d7fdba859R1053
-Robert
> + size = SZ_64K;
> +
> res[num_res].start = smmu->base_address;
> - res[num_res].end = smmu->base_address + SZ_128K - 1;
> + res[num_res].end = smmu->base_address + size - 1;
> res[num_res].flags = IORESOURCE_MEM;
>
> num_res++;
> --
> 1.7.1
>
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Re: [PATCH v7 1/3] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model
On Thu, Jun 8, 2017 at 2:28 PM, Lorenzo Pieralisi
wrote:
> On Tue, May 30, 2017 at 05:33:39PM +0530, Geetha sowjanya wrote:
>> From: Linu Cherian
>>
>> Cavium ThunderX2 implementation doesn't support second page in SMMU
>> register space. Hence, resource size is set as 64k for this model.
>>
>> Signed-off-by: Linu Cherian
>> Signed-off-by: Geetha Sowjanya
>> ---
>> drivers/acpi/arm64/iort.c | 10 +-
>> 1 files changed, 9 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
>> index c5fecf9..bba2b59 100644
>> --- a/drivers/acpi/arm64/iort.c
>> +++ b/drivers/acpi/arm64/iort.c
>> @@ -833,12 +833,20 @@ static void __init arm_smmu_v3_init_resources(struct
>> resource *res,
>> {
>> struct acpi_iort_smmu_v3 *smmu;
>> int num_res = 0;
>> + unsigned long size = SZ_128K;
>>
>> /* Retrieve SMMUv3 specific data */
>> smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
>>
>> + /*
>> + * Override the size, for Cavium ThunderX2 implementation
>> + * which doesn't support the page 1 SMMU register space.
>> + */
>> + if (smmu->model == ACPI_IORT_SMMU_CAVIUM_CN99XX)
>> + size = SZ_64K;
>
> Nit: add a function, say arm_smmu_v3_resource_size() with the logic
> above that by default returns SZ_128K, I do not like this switch
> in the middle of this function.
I will resubmit the patch with suggested changes.
Thanks,
Geetha.
>
> Lorenzo
>
>> +
>> res[num_res].start = smmu->base_address;
>> - res[num_res].end = smmu->base_address + SZ_128K - 1;
>> + res[num_res].end = smmu->base_address + size - 1;
>> res[num_res].flags = IORESOURCE_MEM;
>>
>> num_res++;
>> --
>> 1.7.1
>>
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Re: [PATCH v7 1/3] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model
On Tue, May 30, 2017 at 05:33:39PM +0530, Geetha sowjanya wrote:
> From: Linu Cherian
>
> Cavium ThunderX2 implementation doesn't support second page in SMMU
> register space. Hence, resource size is set as 64k for this model.
>
> Signed-off-by: Linu Cherian
> Signed-off-by: Geetha Sowjanya
> ---
> drivers/acpi/arm64/iort.c | 10 +-
> 1 files changed, 9 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
> index c5fecf9..bba2b59 100644
> --- a/drivers/acpi/arm64/iort.c
> +++ b/drivers/acpi/arm64/iort.c
> @@ -833,12 +833,20 @@ static void __init arm_smmu_v3_init_resources(struct
> resource *res,
> {
> struct acpi_iort_smmu_v3 *smmu;
> int num_res = 0;
> + unsigned long size = SZ_128K;
>
> /* Retrieve SMMUv3 specific data */
> smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
>
> + /*
> + * Override the size, for Cavium ThunderX2 implementation
> + * which doesn't support the page 1 SMMU register space.
> + */
> + if (smmu->model == ACPI_IORT_SMMU_CAVIUM_CN99XX)
> + size = SZ_64K;
Nit: add a function, say arm_smmu_v3_resource_size() with the logic
above that by default returns SZ_128K, I do not like this switch
in the middle of this function.
Lorenzo
> +
> res[num_res].start = smmu->base_address;
> - res[num_res].end = smmu->base_address + SZ_128K - 1;
> + res[num_res].end = smmu->base_address + size - 1;
> res[num_res].flags = IORESOURCE_MEM;
>
> num_res++;
> --
> 1.7.1
>
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[PATCH v7 1/3] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model
From: Linu Cherian
Cavium ThunderX2 implementation doesn't support second page in SMMU
register space. Hence, resource size is set as 64k for this model.
Signed-off-by: Linu Cherian
Signed-off-by: Geetha Sowjanya
---
drivers/acpi/arm64/iort.c | 10 +-
1 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
index c5fecf9..bba2b59 100644
--- a/drivers/acpi/arm64/iort.c
+++ b/drivers/acpi/arm64/iort.c
@@ -833,12 +833,20 @@ static void __init arm_smmu_v3_init_resources(struct
resource *res,
{
struct acpi_iort_smmu_v3 *smmu;
int num_res = 0;
+ unsigned long size = SZ_128K;
/* Retrieve SMMUv3 specific data */
smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
+ /*
+* Override the size, for Cavium ThunderX2 implementation
+* which doesn't support the page 1 SMMU register space.
+*/
+ if (smmu->model == ACPI_IORT_SMMU_CAVIUM_CN99XX)
+ size = SZ_64K;
+
res[num_res].start = smmu->base_address;
- res[num_res].end = smmu->base_address + SZ_128K - 1;
+ res[num_res].end = smmu->base_address + size - 1;
res[num_res].flags = IORESOURCE_MEM;
num_res++;
--
1.7.1
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