Re: [PATCH v8 06/10] iommu/vt-d: Cache virtual command capability register

[Jacob Pan]

On Wed, 18 Dec 2019 11:25:27 +0800
Lu Baolu  wrote:

> Hi,
> 
> On 12/17/19 3:24 AM, Jacob Pan wrote:
> > Virtual command registers are used in the guest only, to prevent
> > vmexit cost, we cache the capability and store it during
> > initialization.
> > 
> > Signed-off-by: Jacob Pan 
> > ---
> >   drivers/iommu/dmar.c| 1 +
> >   include/linux/intel-iommu.h | 4 
> >   2 files changed, 5 insertions(+)
> > 
> > diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c
> > index f2f5d75da94a..3f98dd9ad004 100644
> > --- a/drivers/iommu/dmar.c
> > +++ b/drivers/iommu/dmar.c
> > @@ -953,6 +953,7 @@ static int map_iommu(struct intel_iommu *iommu,
> > u64 phys_addr) warn_invalid_dmar(phys_addr, " returns all ones");
> > goto unmap;
> > }
> > +   iommu->vccap = dmar_readq(iommu->reg + DMAR_VCCAP_REG);
> >   
> > /* the registers might be more than one page */
> > map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),
> > diff --git a/include/linux/intel-iommu.h
> > b/include/linux/intel-iommu.h index ee26989df008..4d25141ec3df
> > 100644 --- a/include/linux/intel-iommu.h
> > +++ b/include/linux/intel-iommu.h
> > @@ -189,6 +189,9 @@
> >   #define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
> >   #define ecap_sc_support(e)((e >> 7) & 0x1) /* Snooping
> > Control */ 
> > +/* Virtual command interface capabilities */
> > +#define vccap_pasid(v) ((v & DMA_VCS_PAS)) /* PASID
> > allocation */  
> 
> Has DMA_VCS_PAS ever been defined?
> 
Good catch, it is in the next patch, need to move the #define here.
Thanks!

> Best regards,
> baolu
> 
>  [...]  

[Jacob Pan]
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Re: [PATCH v8 06/10] iommu/vt-d: Cache virtual command capability register

[Lu Baolu]

Hi,

On 12/17/19 3:24 AM, Jacob Pan wrote:

Virtual command registers are used in the guest only, to prevent
vmexit cost, we cache the capability and store it during initialization.

Signed-off-by: Jacob Pan 
---
  drivers/iommu/dmar.c| 1 +
  include/linux/intel-iommu.h | 4 
  2 files changed, 5 insertions(+)

diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c
index f2f5d75da94a..3f98dd9ad004 100644
--- a/drivers/iommu/dmar.c
+++ b/drivers/iommu/dmar.c
@@ -953,6 +953,7 @@ static int map_iommu(struct intel_iommu *iommu, u64 
phys_addr)
warn_invalid_dmar(phys_addr, " returns all ones");
goto unmap;
}
+   iommu->vccap = dmar_readq(iommu->reg + DMAR_VCCAP_REG);
  
  	/* the registers might be more than one page */

map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index ee26989df008..4d25141ec3df 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -189,6 +189,9 @@
  #define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
  #define ecap_sc_support(e)((e >> 7) & 0x1) /* Snooping Control */
  
+/* Virtual command interface capabilities */

+#define vccap_pasid(v) ((v & DMA_VCS_PAS)) /* PASID allocation */


Has DMA_VCS_PAS ever been defined?

Best regards,
baolu


+
  /* IOTLB_REG */
  #define DMA_TLB_FLUSH_GRANU_OFFSET  60
  #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
@@ -531,6 +534,7 @@ struct intel_iommu {
u64 reg_size; /* size of hw register set */
u64 cap;
u64 ecap;
+   u64 vccap;
u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
raw_spinlock_t  register_lock; /* protect register handling */
int seq_id; /* sequence id of the iommu */


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[PATCH v8 06/10] iommu/vt-d: Cache virtual command capability register

[Jacob Pan]

Virtual command registers are used in the guest only, to prevent
vmexit cost, we cache the capability and store it during initialization.

Signed-off-by: Jacob Pan 
---
 drivers/iommu/dmar.c| 1 +
 include/linux/intel-iommu.h | 4 
 2 files changed, 5 insertions(+)

diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c
index f2f5d75da94a..3f98dd9ad004 100644
--- a/drivers/iommu/dmar.c
+++ b/drivers/iommu/dmar.c
@@ -953,6 +953,7 @@ static int map_iommu(struct intel_iommu *iommu, u64 
phys_addr)
warn_invalid_dmar(phys_addr, " returns all ones");
goto unmap;
}
+   iommu->vccap = dmar_readq(iommu->reg + DMAR_VCCAP_REG);
 
/* the registers might be more than one page */
map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index ee26989df008..4d25141ec3df 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -189,6 +189,9 @@
 #define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
 #define ecap_sc_support(e) ((e >> 7) & 0x1) /* Snooping Control */
 
+/* Virtual command interface capabilities */
+#define vccap_pasid(v) ((v & DMA_VCS_PAS)) /* PASID allocation */
+
 /* IOTLB_REG */
 #define DMA_TLB_FLUSH_GRANU_OFFSET  60
 #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
@@ -531,6 +534,7 @@ struct intel_iommu {
u64 reg_size; /* size of hw register set */
u64 cap;
u64 ecap;
+   u64 vccap;
u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
raw_spinlock_t  register_lock; /* protect register handling */
int seq_id; /* sequence id of the iommu */
-- 
2.7.4

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