Stephen Warren swar...@wwwdotorg.org wrote @ Fri, 1 Nov 2013 17:54:37 +0100:
On 10/31/2013 02:17 AM, Hiroshi Doyu wrote:
Stephen Warren swar...@wwwdotorg.org wrote @ Wed, 30 Oct 2013 23:33:32
+0100:
...
Right.
memory client ID is used to find out MC_SMMU_swgroup_ASID_0
register. This
Mark Rutland mark.rutl...@arm.com wrote @ Thu, 31 Oct 2013 18:31:33 +0100:
Assuming swgroup is memory client ID, why can't the driver just
create a list/... of known swgroups at runtime, based on the swgroup
values that each device uses, which would presumably be either
hard-coded in the
On 10/31/2013 02:17 AM, Hiroshi Doyu wrote:
Stephen Warren swar...@wwwdotorg.org wrote @ Wed, 30 Oct 2013 23:33:32
+0100:
...
Right.
memory client ID is used to find out MC_SMMU_swgroup_ASID_0
register. This register is used to associate swgroup to address
space(AS). swgroup == H/W. swgroup
Stephen Warren swar...@wwwdotorg.org wrote @ Wed, 30 Oct 2013 23:33:32 +0100:
+ are required. This unique ID info can be used to calculate
+ MC_SMMU_SWGROUP name_ASID_0 offset and HOTRESET bit.
I'm afraid I still don't quite understand what a swgroup is.
IIUC, the HW works like this
On Fri, Oct 18, 2013 at 11:26:51AM +0100, Hiroshi Doyu wrote:
This provides the info about which H/W Accelerators are supported on
Tegra SoC. This info is passed from DT. This is necessary to have the
unified SMMU driver among Tegra SoCs. Instead of using platform data,
DT passes
On Thu, Oct 31, 2013 at 05:31:33PM +, Mark Rutland wrote:
On Wed, Oct 30, 2013 at 10:33:32PM +, Stephen Warren wrote:
I'm afraid I still don't quite understand what a swgroup is.
IIUC, the HW works like this based on comments in a previous patch:
Each bus-master attached to
On 10/24/2013 02:58 AM, Grant Likely wrote:
On Fri, 18 Oct 2013 13:26:51 +0300, Hiroshi Doyu hd...@nvidia.com wrote:
This provides the info about which H/W Accelerators are supported on
Tegra SoC. This info is passed from DT. This is necessary to have the
unified SMMU driver among Tegra SoCs.
On 10/18/2013 04:26 AM, Hiroshi Doyu wrote:
This provides the info about which H/W Accelerators are supported on
Tegra SoC. This info is passed from DT. This is necessary to have the
unified SMMU driver among Tegra SoCs. Instead of using platform data,
DT passes nvidia,swgroups now. DT is
