rdan Crouse
>>>Sent: Wednesday, January 04, 2017 3:59 AM
>>>To: Rob Clark
>>>Cc: Will Deacon ; iommu@lists.linux-foundation.org;
>>>linux-arm-...@vger.kernel.org; Sricharan R
>>>
>>>Subject: Re: [RFC 2/3] iommu/arm-smmu: Add qcom implementation
>
Rob Clark
>>Cc: Will Deacon ; iommu@lists.linux-foundation.org;
>>linux-arm-...@vger.kernel.org; Sricharan R
>>
>>Subject: Re: [RFC 2/3] iommu/arm-smmu: Add qcom implementation
>>
>>On Tue, Jan 03, 2017 at 04:30:55PM -0500, Rob Clark wrote:
>>> At least
m-...@vger.kernel.org; Sricharan R
>
>Subject: Re: [RFC 2/3] iommu/arm-smmu: Add qcom implementation
>
>On Tue, Jan 03, 2017 at 04:30:55PM -0500, Rob Clark wrote:
>> At least on the db820c I have, with the firmware I have, I'm not seeing
>> the SS bit set, even thoug
On Tue, Jan 03, 2017 at 04:30:55PM -0500, Rob Clark wrote:
> At least on the db820c I have, with the firmware I have, I'm not seeing
> the SS bit set, even though the iommu is in a stalled state. So for
> this implementation ignore not having SS bit set.
The SS bit gets set if SCTLR.CFCFG is set
At least on the db820c I have, with the firmware I have, I'm not seeing
the SS bit set, even though the iommu is in a stalled state. So for
this implementation ignore not having SS bit set.
Signed-off-by: Rob Clark
---
drivers/iommu/arm-smmu.c | 6 ++
1 file changed, 6 insertions(+)
diff -
