On Fri, May 12, 2017 at 01:11:02PM +0100, Jean-Philippe Brucker wrote:
> Hi Yi,
>
> On 26/04/17 11:12, Liu, Yi L wrote:
> > From: "Liu, Yi L"
> >
> > This patch adds VFIO_IOMMU_TLB_INVALIDATE to propagate IOMMU TLB
> > invalidate request from guest to host.
> >
> > In
On Fri, May 12, 2017 at 03:59:14PM -0600, Alex Williamson wrote:
> On Wed, 26 Apr 2017 18:11:58 +0800
> "Liu, Yi L" wrote:
>
> > From: Jacob Pan
> >
> > Virtual IOMMU was proposed to support Shared Virtual Memory (SVM) use
> > case in the
On 14/05/17 19:27, Thomas Gleixner wrote:
> To enable smp_processor_id() and might_sleep() debug checks earlier, it's
> required to add system states between SYSTEM_BOOTING and SYSTEM_RUNNING.
>
> Adjust the system_state check in of_iommu_driver_present() to handle the
> extra states.
FWIW,
On Fri, May 12, 2017 at 03:58:43PM -0600, Alex Williamson wrote:
> On Wed, 26 Apr 2017 18:12:04 +0800
> "Liu, Yi L" wrote:
>
> > From: "Liu, Yi L"
> >
> > This patch adds VFIO_IOMMU_TLB_INVALIDATE to propagate IOMMU TLB
> > invalidate request from
Hi Jean,
On 27.02.2017 20:54, Jean-Philippe Brucker wrote:
@@ -1213,17 +1356,59 @@ static void arm_smmu_free_cd_tables(struct
arm_smmu_master_data *master)
__maybe_unused
static int arm_smmu_alloc_cd(struct arm_smmu_master_data *master)
{
+ int ssid;
+ int i, ret;
struct
On 14/05/17 11:12, Liu, Yi L wrote:
> On Fri, May 12, 2017 at 01:11:02PM +0100, Jean-Philippe Brucker wrote:
>> Hi Yi,
>>
>> On 26/04/17 11:12, Liu, Yi L wrote:
>>> From: "Liu, Yi L"
>>>
>>> This patch adds VFIO_IOMMU_TLB_INVALIDATE to propagate IOMMU TLB
>>> invalidate
On Fri, 12 May 2017 15:59:29 -0600
Alex Williamson wrote:
> > + if (pasidt_binfo->size >= intel_iommu_get_pts(iommu)) {
> > + pr_err("Invalid gPASID table size %llu, host size
> > %lu\n",
> > + pasidt_binfo->size,
> > +
Hi Sricharan,
On Wed, May 03, 2017 at 03:54:59PM +0530, Sricharan R wrote:
> On 5/3/2017 3:24 PM, Robin Murphy wrote:
> > On 02/05/17 19:35, Geert Uytterhoeven wrote:
> >> On Fri, Feb 3, 2017 at 4:48 PM, Sricharan R
> >> wrote:
> >>> From: Laurent Pinchart
On Sun, May 14, 2017 at 08:27:26PM +0200, Thomas Gleixner wrote:
> To enable smp_processor_id() and might_sleep() debug checks earlier, it's
> required to add system states between SYSTEM_BOOTING and SYSTEM_RUNNING.
>
> Adjust the system_state checks in dmar_parse_one_atsr() and
>
On Tue, Apr 18, 2017 at 04:19:21PM -0500, Tom Lendacky wrote:
> Boot data (such as EFI related data) is not encrypted when the system is
> booted because UEFI/BIOS does not run with SME active. In order to access
> this data properly it needs to be mapped decrypted.
>
> The early_memremap()
On Tue, Apr 18, 2017 at 04:18:48PM -0500, Tom Lendacky wrote:
> Add a function that will determine if a supplied physical address matches
> the address of an EFI table.
>
> Signed-off-by: Tom Lendacky
> ---
> drivers/firmware/efi/efi.c | 33
On 11/05/17 19:27, Aaron Sierra wrote:
> - Original Message -
>> From: "Robin Murphy"
>> To: "Aaron Sierra" , "Joerg Roedel"
>> Cc: "iommu" , "Nate Watterson"
>>
>>
Hi Sricharan,
On Wednesday 03 May 2017 15:54:59 Sricharan R wrote:
> On 5/3/2017 3:24 PM, Robin Murphy wrote:
> > On 02/05/17 19:35, Geert Uytterhoeven wrote:
> >> On Fri, Feb 3, 2017 at 4:48 PM, Sricharan R wrote:
> >>> From: Laurent Pinchart
> >>>
>
Hi Sricharan,
On Monday 15 May 2017 23:37:16 Laurent Pinchart wrote:
> On Wednesday 03 May 2017 15:54:59 Sricharan R wrote:
> > On 5/3/2017 3:24 PM, Robin Murphy wrote:
> >> On 02/05/17 19:35, Geert Uytterhoeven wrote:
> >>> On Fri, Feb 3, 2017 at 4:48 PM, Sricharan R wrote:
> From: Laurent
On 15/05/17 13:47, Tomasz Nowicki wrote:
> Hi Jean,
>
> On 27.02.2017 20:54, Jean-Philippe Brucker wrote:
>> @@ -1213,17 +1356,59 @@ static void arm_smmu_free_cd_tables(struct
>> arm_smmu_master_data *master)
>> __maybe_unused
>> static int arm_smmu_alloc_cd(struct arm_smmu_master_data *master)
Hi Laurent,
On 2017-05-16 03:04, Laurent Pinchart wrote:
Hi Sricharan,
On Monday 15 May 2017 23:37:16 Laurent Pinchart wrote:
On Wednesday 03 May 2017 15:54:59 Sricharan R wrote:
> On 5/3/2017 3:24 PM, Robin Murphy wrote:
>> On 02/05/17 19:35, Geert Uytterhoeven wrote:
>>> On Fri, Feb 3, 2017
Hi Will,
On 2017-05-15 19:52, Will Deacon wrote:
Hi Sricharan,
On Wed, May 03, 2017 at 03:54:59PM +0530, Sricharan R wrote:
On 5/3/2017 3:24 PM, Robin Murphy wrote:
> On 02/05/17 19:35, Geert Uytterhoeven wrote:
>> On Fri, Feb 3, 2017 at 4:48 PM, Sricharan R wrote:
DT changes should go to DT list.
On Fri, May 12, 2017 at 7:41 AM, Geetha sowjanya
wrote:
> From: Linu Cherian
>
> Cavium ThunderX2 SMMU implementation doesn't support page 1 register space
> and PAGE0_REGS_ONLY option is enabled as an errata
On Sat, May 6, 2017 at 11:00 AM, Oza Oza wrote:
> On Fri, May 5, 2017 at 8:55 PM, Robin Murphy wrote:
>> On 04/05/17 19:41, Oza Oza wrote:
>> [...]
> 5) leaves scope of adding PCI flag handling for inbound memory
> by the new function.
While returning EPROBE_DEFER for iommu masters
take in to account of iommu nodes that could be
marked in DT as 'status=disabled', in which case
simply return NULL and let the master's probe
continue rather than deferring.
Signed-off-by: Sricharan R
Tested-by: Will
this patch reserves the IOVA for PCI masters.
ARM64 based SOCs may have scattered memory banks.
such as iproc based SOC has
<0x 0x8000 0x0 0x8000>, /* 2G @ 2G */
<0x0008 0x8000 0x3 0x8000>, /* 14G @ 34G */
<0x0090 0x 0x4 0x>, /* 16G @ 576G */
current device framework and OF framework integration assumes
dma-ranges in a way where memory-mapped devices define their
dma-ranges. (child-bus-address, parent-bus-address, length).
of_dma_configure is specifically written to take care of memory
mapped devices. but no implementation exists for
current device framework and OF framework integration assumes
dma-ranges in a way where memory-mapped devices define their
dma-ranges. (child-bus-address, parent-bus-address, length).
of_dma_configure is specifically written to take care of memory
mapped devices. but no implementation exists for
It is possible that PCI device supports 64-bit DMA addressing,
and thus it's driver sets device's dma_mask to DMA_BIT_MASK(64),
however PCI host bridge may have limitations on the inbound
transaction addressing.
This is particularly problematic on ARM/ARM64 SOCs where the
IOMMU (i.e. SMMU)
On Sat, May 13, 2017 at 4:47 AM, shameer
wrote:
> Signed-off-by: shameer
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
When __iommu_dma_map() and iommu_dma_free_iova() are called from
iommu_dma_get_msi_page(), various iova_*() helpers are still invoked in
the process, whcih is unwise since they access a different member of the
union (the iova_domain) from that which was last written, and there's no
guarantee that
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