Re: [PATCH v7 20/36] x86, mpparse: Use memremap to map the mpf and mpc data

On Fri, Jun 16, 2017 at 01:53:38PM -0500, Tom Lendacky wrote: > The SMP MP-table is built by UEFI and placed in memory in a decrypted > state. These tables are accessed using a mix of early_memremap(), > early_memunmap(), phys_to_virt() and virt_to_phys(). Change all accesses > to use

Re: [PATCH v7 08/36] x86/mm: Add support to enable SME in early boot processing

On Fri, 16 Jun 2017, Tom Lendacky wrote: > diff --git a/arch/x86/include/asm/mem_encrypt.h > b/arch/x86/include/asm/mem_encrypt.h > index a105796..988b336 100644 > --- a/arch/x86/include/asm/mem_encrypt.h > +++ b/arch/x86/include/asm/mem_encrypt.h > @@ -15,16 +15,24 @@ > > #ifndef __ASSEMBLY__

Re: [PATCH v7 10/36] x86/mm: Provide general kernel support for memory encryption

On Wed, Jun 21, 2017 at 09:18:59AM +0200, Thomas Gleixner wrote: > That looks wrong. It's not decrypted it's rather unencrypted, right? Yeah, it previous versions of the patchset, "decrypted" and "unencrypted" were both present so we settled on "decrypted" for the nomenclature. --

Re: [PATCH v7 10/36] x86/mm: Provide general kernel support for memory encryption

On Fri, 16 Jun 2017, Tom Lendacky wrote: > > +#ifndef pgprot_encrypted > +#define pgprot_encrypted(prot) (prot) > +#endif > + > +#ifndef pgprot_decrypted That looks wrong. It's not decrypted it's rather unencrypted, right? Thanks, tglx

Re: [PATCH v8 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126

Hi Will, On Tue, Jun 20, 2017 at 11:30 PM, Will Deacon wrote: > On Tue, Jun 20, 2017 at 07:47:39PM +0530, Geetha sowjanya wrote: >> From: Geetha Sowjanya >> >> Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq >>

Re: [PATCH v7 07/36] x86/mm: Don't use phys_to_virt in ioremap() if SME is active

On Fri, 16 Jun 2017, Tom Lendacky wrote: > Currently there is a check if the address being mapped is in the ISA > range (is_ISA_range()), and if it is then phys_to_virt() is used to > perform the mapping. When SME is active, however, this will result > in the mapping having the encryption bit set

Re: [PATCH v7 23/36] x86, realmode: Decrypt trampoline area if memory encryption is active

On Fri, Jun 16, 2017 at 01:54:12PM -0500, Tom Lendacky wrote: > When Secure Memory Encryption is enabled, the trampoline area must not > be encrypted. A CPU running in real mode will not be able to decrypt > memory that has been encrypted because it will not be able to use addresses > with the

Re: [PATCH v8 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126

On 21/06/17 10:08, Will Deacon wrote: > Hi Geetha, > > On Wed, Jun 21, 2017 at 12:09:45PM +0530, Geetha Akula wrote: >> On Tue, Jun 20, 2017 at 11:30 PM, Will Deacon wrote: >>> On Tue, Jun 20, 2017 at 07:47:39PM +0530, Geetha sowjanya wrote: From: Geetha Sowjanya

Re: [PATCH v7 25/36] swiotlb: Add warnings for use of bounce buffers with SME

On Fri, Jun 16, 2017 at 01:54:36PM -0500, Tom Lendacky wrote: > Add warnings to let the user know when bounce buffers are being used for > DMA when SME is active. Since the bounce buffers are not in encrypted > memory, these notifications are to allow the user to determine some > appropriate

Re: [PATCH 1/1] iommu/arm-smmu-v3: replace writel with writel_relaxed in queue_inc_prod

On Wed, Jun 21, 2017 at 09:28:23AM +0800, Leizhen (ThunderTown) wrote: > On 2017/6/20 19:35, Robin Murphy wrote: > > On 20/06/17 12:04, Zhen Lei wrote: > >> This function is protected by spinlock, and the latter will do memory > >> barrier implicitly. So that we can safely use writel_relaxed. In

Re: [PATCH v8 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126

Hi Geetha, On Wed, Jun 21, 2017 at 12:09:45PM +0530, Geetha Akula wrote: > On Tue, Jun 20, 2017 at 11:30 PM, Will Deacon wrote: > > On Tue, Jun 20, 2017 at 07:47:39PM +0530, Geetha sowjanya wrote: > >> From: Geetha Sowjanya > >> > >> Cavium

Re: [PATCH v3] iommu/arm-smmu: Plumb in new ACPI identifiers

On Mon, Jun 19, 2017 at 04:41:56PM +0100, Robin Murphy wrote: > Revision C of IORT now allows us to identify ARM MMU-401 and the Cavium > ThunderX implementation. Wire them up so that we can probe these models > once firmware starts using the new codes in place of generic ones, and > so that the

Re: [PATCH v7 24/36] x86, swiotlb: Add memory encryption support

On Fri, Jun 16, 2017 at 01:54:24PM -0500, Tom Lendacky wrote: > Since DMA addresses will effectively look like 48-bit addresses when the > memory encryption mask is set, SWIOTLB is needed if the DMA mask of the > device performing the DMA does not support 48-bits. SWIOTLB will be > initialized to

[RESEND PATCH 3/4] iommu: add qcom_iommu

An iommu driver for Qualcomm "B" family devices which do implement the ARM SMMU spec, but not in a way that is compatible with how the arm-smmu driver is designed. It seems SMMU_SCR1.GASRAE=1 so the global register space is not accessible. This means it needs to get configuration from devicetree

[RESEND PATCH 4/4] iommu: qcom: initialize secure page table

From: Stanimir Varbanov This basically gets the secure page table size, allocates memory for secure pagetables and passes the physical address to the trusted zone. Signed-off-by: Stanimir Varbanov Signed-off-by: Rob Clark

[RESEND PATCH 2/4] iommu: arm-smmu: split out register defines

I want to re-use some of these for qcom_iommu, which has (roughly) the same context-bank registers. Signed-off-by: Rob Clark --- drivers/iommu/arm-smmu-regs.h | 227 ++ drivers/iommu/arm-smmu.c | 203

[RESEND PATCH 1/4] Docs: dt: document qcom iommu bindings

Cc: devicet...@vger.kernel.org Signed-off-by: Rob Clark Reviewed-by: Rob Herring --- .../devicetree/bindings/iommu/qcom,iommu.txt | 121 + 1 file changed, 121 insertions(+) create mode 100644

[RESEND PATCH 0/4] iommu: add qcom_iommu for early "B" family devices

An iommu driver for Qualcomm "B" family devices which do not implement the ARM SMMU spec in a way that is compatible with the arm-smmu driver. No change since last time, other than Riku's tested-by. Rob Clark (3): Docs: dt: document qcom iommu bindings iommu: arm-smmu: split out register

Re: [PATCH v7 06/36] x86/mm: Add Secure Memory Encryption (SME) support

On 6/20/2017 3:49 PM, Thomas Gleixner wrote: On Fri, 16 Jun 2017, Tom Lendacky wrote: +config ARCH_HAS_MEM_ENCRYPT + def_bool y + depends on X86 That one is silly. The config switch is in the x86 KConfig file, so X86 is on. If you intended to move this to some generic place

Re: new dma-mapping tree, was Re: clean up and modularize arch dma_mapping interface V2

Hi Christoph, On 2017-06-20 15:16, Christoph Hellwig wrote: On Tue, Jun 20, 2017 at 11:04:00PM +1000, Stephen Rothwell wrote: git://git.linaro.org/people/mszyprowski/linux-dma-mapping.git#dma-mapping-next Contacts: Marek Szyprowski and Kyungmin Park (cc'd) I have called your tree

Re: [PATCH v1 3/3] iommu/amd: Optimize the IOMMU queue flush

On Wed, 2017-06-21 at 12:01 -0500, Tom Lendacky wrote: > On 6/21/2017 11:20 AM, Jan Vesely wrote: > > Hi Arindam, > > > > has this patch been replaced by Joerg's "[PATCH 0/7] iommu/amd: > > Optimize iova queue flushing" series? > > Yes, Joerg's patches replaced this patch. He applied just the

Re: [PATCH v7 08/36] x86/mm: Add support to enable SME in early boot processing

On Wed, 21 Jun 2017, Tom Lendacky wrote: > On 6/21/2017 10:38 AM, Thomas Gleixner wrote: > > /* > > * Sanitize CPU configuration and retrieve the modifier > > * for the initial pgdir entry which will be programmed > > * into CR3. Depends on enabled SME encryption, normally 0. >

Re: clean up and modularize arch dma_mapping interface V2

On 06/16/2017 11:10 AM, Christoph Hellwig wrote: Hi all, for a while we have a generic implementation of the dma mapping routines that call into per-arch or per-device operations. But right now there still are various bits in the interfaces where don't clearly operate on these ops. This

Re: [PATCH v6 26/34] iommu/amd: Allow the AMD IOMMU to work with memory encryption

On 6/21/2017 11:59 AM, Borislav Petkov wrote: On Wed, Jun 21, 2017 at 05:37:22PM +0200, Joerg Roedel wrote: Do you mean this is like the last exception case in that document above: " - Pointers to data structures in coherent memory which might be modified by I/O devices can, sometimes,

Re: [PATCH v7 25/36] swiotlb: Add warnings for use of bounce buffers with SME

On 6/21/2017 5:50 AM, Borislav Petkov wrote: On Fri, Jun 16, 2017 at 01:54:36PM -0500, Tom Lendacky wrote: Add warnings to let the user know when bounce buffers are being used for DMA when SME is active. Since the bounce buffers are not in encrypted memory, these notifications are to allow the

Re: [PATCH v7 08/36] x86/mm: Add support to enable SME in early boot processing

On Wed, 21 Jun 2017, Tom Lendacky wrote: > On 6/21/2017 2:16 AM, Thomas Gleixner wrote: > > Why is this an unconditional function? Isn't the mask simply 0 when the MEM > > ENCRYPT support is disabled? > > I made it unconditional because of the call from head_64.S. I can't make > use of the C

Re: [PATCH 0/8] io-pgtable lock removal

On Wed, Jun 14, 2017 at 05:40:30PM -0700, Ray Jui wrote: > With the NVMf target test with 4 SSDs, fio based test, random read, 4k, > 8 jobs: > > Without IOMMU: > > IOPS = 1080K > > With IOMMU, but without your latest patch: > > IOPS = 520K > > With IOMMU and your latest patch: > > IOPS =

Re: [patch 02/55] iommu/amd: Add name to irq chip

On Tue, Jun 20, 2017 at 01:37:02AM +0200, Thomas Gleixner wrote: > Add the missing name, so debugging will work proper. > > Signed-off-by: Thomas Gleixner > Cc: Joerg Roedel > Cc: iommu@lists.linux-foundation.org Acked-by: Joerg Roedel

Re: [patch 03/55] iommu/vt-d: Add name to irq chip

On Tue, Jun 20, 2017 at 01:37:03AM +0200, Thomas Gleixner wrote: > Add the missing name, so debugging will work proper. > > Signed-off-by: Thomas Gleixner > Cc: Joerg Roedel > Cc: iommu@lists.linux-foundation.org Acked-by: Joerg Roedel

Re: [patch 11/55] iommu/vt-d: Use named irq domain interface

On Tue, Jun 20, 2017 at 01:37:11AM +0200, Thomas Gleixner wrote: > Signed-off-by: Thomas Gleixner > Cc: Joerg Roedel > Cc: iommu@lists.linux-foundation.org Acked-by: Joerg Roedel ___ iommu mailing

Re: [patch 12/55] iommu/amd: Use named irq domain interface

On Tue, Jun 20, 2017 at 01:37:12AM +0200, Thomas Gleixner wrote: > Signed-off-by: Thomas Gleixner > Cc: Joerg Roedel > Cc: iommu@lists.linux-foundation.org Acked-by: Joerg Roedel ___ iommu mailing

Re: [PATCH v7 07/36] x86/mm: Don't use phys_to_virt in ioremap() if SME is active

On 6/21/2017 2:37 AM, Thomas Gleixner wrote: On Fri, 16 Jun 2017, Tom Lendacky wrote: Currently there is a check if the address being mapped is in the ISA range (is_ISA_range()), and if it is then phys_to_virt() is used to perform the mapping. When SME is active, however, this will result in

Re: [PATCH v7 07/36] x86/mm: Don't use phys_to_virt in ioremap() if SME is active

On 6/20/2017 3:55 PM, Thomas Gleixner wrote: On Fri, 16 Jun 2017, Tom Lendacky wrote: Currently there is a check if the address being mapped is in the ISA range (is_ISA_range()), and if it is then phys_to_virt() is used to perform the mapping. When SME is active, however, this will result in

Re: [PATCH v7 08/36] x86/mm: Add support to enable SME in early boot processing

On 6/21/2017 2:16 AM, Thomas Gleixner wrote: On Fri, 16 Jun 2017, Tom Lendacky wrote: diff --git a/arch/x86/include/asm/mem_encrypt.h b/arch/x86/include/asm/mem_encrypt.h index a105796..988b336 100644 --- a/arch/x86/include/asm/mem_encrypt.h +++ b/arch/x86/include/asm/mem_encrypt.h @@ -15,16

Re: [PATCH v6 26/34] iommu/amd: Allow the AMD IOMMU to work with memory encryption

On Wed, Jun 21, 2017 at 05:37:22PM +0200, Joerg Roedel wrote: > > Do you mean this is like the last exception case in that document above: > > > > " > > - Pointers to data structures in coherent memory which might be modified > > by I/O devices can, sometimes, legitimately be volatile. A

Re: [PATCH v1 3/3] iommu/amd: Optimize the IOMMU queue flush

On 6/21/2017 11:20 AM, Jan Vesely wrote: Hi Arindam, has this patch been replaced by Joerg's "[PATCH 0/7] iommu/amd: Optimize iova queue flushing" series? Yes, Joerg's patches replaced this patch. He applied just the first two patches of this series. Thanks, Tom Jan On Thu, 2017-06-08

Re: [PATCH v1 3/3] iommu/amd: Optimize the IOMMU queue flush

Hi Arindam, has this patch been replaced by Joerg's "[PATCH 0/7] iommu/amd: Optimize iova queue flushing" series? Jan On Thu, 2017-06-08 at 22:33 +0200, Jan Vesely wrote: > On Tue, 2017-06-06 at 10:02 +, Nath, Arindam wrote: > > > -Original Message- > > > From: Lendacky, Thomas > >