On 10/14/18 3:52 AM, Christoph Hellwig wrote:
We already build the swiotlb code for 32b-t kernels with PAE support,
but the code to actually use swiotlb has only been enabled for 64-bit
kernel for an unknown reason.
Before Linux 4.18 we papers over this fact because the networking code,
the
[Replying with my personal address because we're having SMTP issues]
On 12/10/2018 20:41, Bjorn Helgaas wrote:
> s/iommu/IOMMU/ in subject
>
> On Fri, Oct 12, 2018 at 03:59:13PM +0100, Jean-Philippe Brucker wrote:
>> Using the iommu-map binding, endpoints in a given PCI domain can be
>> managed
[Replying with my personal address because we're having SMTP issues]
On 15/10/2018 11:52, Michael S. Tsirkin wrote:
> On Fri, Oct 12, 2018 at 02:41:59PM -0500, Bjorn Helgaas wrote:
>> s/iommu/IOMMU/ in subject
>>
>> On Fri, Oct 12, 2018 at 03:59:13PM +0100, Jean-Philippe Brucker wrote:
>>> Using
On Thu, 11 Oct 2018 12:09:16 -0700
Jerry Snitselaar wrote:
> On Fri Oct 05 18, Jacob Pan wrote:
> >On Thu, 4 Oct 2018 13:57:24 -0700
> >Jerry Snitselaar wrote:
> >
> >> >
> >> >On Tue, Oct 02, 2018 at 10:25:29AM -0700, Jerry Snitselaar
> >> >wrote:
> >> >> I've been trying to track down a
On Wed, 3 Oct 2018 18:52:16 +0100
Jean-Philippe Brucker wrote:
> On 26/09/2018 23:35, Jacob Pan wrote:
> > On Thu, 20 Sep 2018 18:00:39 +0100
> > Jean-Philippe Brucker wrote:
> >
> >> +
> >> +static int io_mm_attach(struct iommu_domain *domain, struct device
> >> *dev,
> >> +
Hi,
On 10/15/2018 04:50 PM, Xu Zaibo wrote:
Hi,
On 2018/10/15 10:48, Lu Baolu wrote:
Hi,
On 10/13/2018 04:25 PM, Xu Zaibo wrote:
Hi,
On 2018/10/12 13:16, Lu Baolu wrote:
Hi,
The Mediate Device is a framework for fine-grained physical device
sharing across the isolated domains. Currently
Hi,
On 2018/10/15 10:48, Lu Baolu wrote:
Hi,
On 10/13/2018 04:25 PM, Xu Zaibo wrote:
Hi,
On 2018/10/12 13:16, Lu Baolu wrote:
Hi,
The Mediate Device is a framework for fine-grained physical device
sharing across the isolated domains. Currently the mdev framework
is designed to be
From: Hai Nguyen Pham
Support the r8a77990 IPMMU and update IPMMU_OF_DECLARE to hook up
the updated compat string.
Signed-off-by: Hai Nguyen Pham
Signed-off-by: Kazuya Mizuguchi
[simon: rebased; dropped no longer required IOMMU_OF_DECLARE hunk]
Signed-off-by: Simon Horman
---
ITS translation register map:
0x-0x003C Reserved
0x0040 GITS_TRANSLATER
0x0044-0xFFFC Reserved
The standard GITS_TRANSLATER register in ITS is only 4 bytes, but Hisilicon
expands the next 4 bytes to carry some IMPDEF information. That means, 8 bytes
data will be written to
Hello!
On 10/15/2018 12:55 PM, Simon Horman wrote:
> From: Hai Nguyen Pham
>
> Support the r8a77990 IPMMU and update IPMMU_OF_DECLARE to hook up
That macro is gone, you need to update the description.
> the updated compat string.
>
> Signed-off-by: Hai Nguyen Pham
> Signed-off-by:
On Fri, Oct 12, 2018 at 02:41:59PM -0500, Bjorn Helgaas wrote:
> s/iommu/IOMMU/ in subject
>
> On Fri, Oct 12, 2018 at 03:59:13PM +0100, Jean-Philippe Brucker wrote:
> > Using the iommu-map binding, endpoints in a given PCI domain can be
> > managed by different IOMMUs. Some virtual machines may
On 15/10/2018 09:36, Zhen Lei wrote:
ITS translation register map:
0x-0x003C Reserved
0x0040 GITS_TRANSLATER
0x0044-0xFFFC Reserved
Can you add a better opening than the ITS translation register map?
The standard GITS_TRANSLATER register in ITS is only 4 bytes, but
From: Hanna Hawa
This patch introduce the smmu_writeq_relaxed/smmu_readq_relaxed
helpers, as preparation to add specific Marvell work-around for
accessing 64bit width registers of ARM SMMU.
Signed-off-by: Hanna Hawa
---
drivers/iommu/arm-smmu.c | 36 +++-
1
From: Hanna Hawa
Add SMMU node for Marvell Armada-AP806 SOC.
Signed-off-by: Hanna Hawa
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
On 15/10/18 13:00, han...@marvell.com wrote:
From: Hanna Hawa
Add specific compatible string for Marvell usage due errata of
accessing 64bit registers of ARM SMMU, in AP806.
AP806 SOC use the generic ARM-MMU500, and there's no specific
implementation of Marvell, this compatible is used for
Hi Hanna,
On 15/10/18 13:00, han...@marvell.com wrote:
From: Hanna Hawa
Due to erratum #582743, the Marvell Armada-AP806 can't access 64bit
to ARM SMMUv2 registers.
This patch split the writeq/readq to two accesses of writel/readl.
Note that separate writes/reads to 2 is not problem regards
On 12/10/18 20:41, Bjorn Helgaas wrote:
s/iommu/IOMMU/ in subject
On Fri, Oct 12, 2018 at 03:59:13PM +0100, Jean-Philippe Brucker wrote:
Using the iommu-map binding, endpoints in a given PCI domain can be
managed by different IOMMUs. Some virtual machines may allow a subset of
endpoints to
From: Hanna Hawa
Add specific compatible string for Marvell usage due errata of
accessing 64bit registers of ARM SMMU, in AP806.
AP806 SOC use the generic ARM-MMU500, and there's no specific
implementation of Marvell, this compatible is used for errata only.
Signed-off-by: Hanna Hawa
---
From: Hanna Hawa
Due to erratum #582743, the Marvell Armada-AP806 can't access 64bit
to ARM SMMUv2 registers.
This patch split the writeq/readq to two accesses of writel/readl.
Note that separate writes/reads to 2 is not problem regards to atomicity,
because the driver use the readq/writeq
From: Hanna Hawa
This series add support for IOMMU for AP806, including workaround
for accessing ARM SMMU 64bit registers.
AP-806 can't access SMMU registers with 64bit width, this patches split
the readq/writeq for 32bit access, due to erratanum #582743.
Hanna Hawa (4):
iommu/arm-smmu:
On 15/10/18 09:36, Zhen Lei wrote:
ITS translation register map:
0x-0x003C Reserved
0x0040 GITS_TRANSLATER
0x0044-0xFFFC Reserved
The standard GITS_TRANSLATER register in ITS is only 4 bytes, but Hisilicon
expands the next 4 bytes to carry some IMPDEF information. That means, 8
On Mon, Oct 15, 2018 at 04:36:16PM +0800, Zhen Lei wrote:
> ITS translation register map:
> 0x-0x003C Reserved
> 0x0040GITS_TRANSLATER
> 0x0044-0xFFFC Reserved
>
> The standard GITS_TRANSLATER register in ITS is only 4 bytes, but Hisilicon
> expands the next 4 bytes to carry
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