On Thu, Jul 25, 2019 at 2:24 PM Dmitry Osipenko wrote:
>
> 25.07.2019 5:41, YueHaibing пишет:
> > If IOMMU_SUPPORT is not set, and COMPILE_TEST is y,
> > IOMMU_IOVA may be set to m. So building will fails:
> >
> > drivers/staging/media/tegra-vde/iommu.o: In function `tegra_vde_iommu_map':
> >
Quoting Sai Prakash Ranjan (2019-09-20 01:04:29)
> From: Vivek Gautam
>
> Add reset hook for sdm845 based platforms to turn off
> the wait-for-safe sequence.
>
> Understanding how wait-for-safe logic affects USB and UFS performance
> on MTP845 and DB845 boards:
>
> Qcom's implementation of
20.09.2019 22:32, Arnd Bergmann пишет:
> On Thu, Jul 25, 2019 at 2:24 PM Dmitry Osipenko wrote:
>>
>> 25.07.2019 5:41, YueHaibing пишет:
>>> If IOMMU_SUPPORT is not set, and COMPILE_TEST is y,
>>> IOMMU_IOVA may be set to m. So building will fails:
>>>
>>> drivers/staging/media/tegra-vde/iommu.o:
> On 10. Sep 2019, at 19:49, Filippo Sironi wrote:
>
> iommu_map_page calls into __domain_flush_pages, which requires the
> domain lock since it traverses the device list, which the lock protects.
>
> Signed-off-by: Filippo Sironi
> ---
> drivers/iommu/amd_iommu.c | 5 +
> 1 file
On Fri, Sep 20, 2019 at 08:07:38AM +0800, Guo Ren wrote:
> On Thu, Sep 19, 2019 at 11:18 PM Jean-Philippe Brucker
> wrote:
>
> >
> > The SMMU does support PCI Virtual Function - an hypervisor can assign a
> > VF to a guest, and let that guest partition the VF into smaller contexts
> > by using
Hi Will,
As a follow-up of the VFIO/IOMMU/PCI "Dual Stage SMMUv3 Status"
session, please find some further justifications about the
SMMUv3 nested stage enablement series.
In the text below, I only talk about use cases featuring
VFIO assigned devices where the physical IOMMU is actually
involved.
On 2019-09-20 01:30, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2019-09-19 11:54:27)
On 2019-09-19 08:48, Sai Prakash Ranjan wrote:
> On 2019-09-19 05:55, Bjorn Andersson wrote:
>> In the transition to this new design we lost the ability to
>> enable/disable the safe toggle per board,
From: Vivek Gautam
There are scnenarios where drivers are required to make a
scm call in atomic context, such as in one of the qcom's
arm-smmu-500 errata [1].
[1] ("https://source.codeaurora.org/quic/la/kernel/msm-4.9/
tree/drivers/iommu/arm-smmu.c?h=msm-4.9#n4842")
Signed-off-by: Vivek
From: Vivek Gautam
Add reset hook for sdm845 based platforms to turn off
the wait-for-safe sequence.
Understanding how wait-for-safe logic affects USB and UFS performance
on MTP845 and DB845 boards:
Qcom's implementation of arm,mmu-500 adds a WAIT-FOR-SAFE logic
to address under-performance
From: Vivek Gautam
Qcom's smmu-500 needs to toggle wait-for-safe sequence to
handle TLB invalidation sync's.
Few firmwares allow doing that through SCM interface.
Add API to toggle wait for safe from firmware through a
SCM call.
Signed-off-by: Vivek Gautam
Reviewed-by: Bjorn Andersson
Previous version of the patches are at [1]:
QCOM's implementation of smmu-500 on sdm845 adds a hardware logic called
wait-for-safe. This logic helps in meeting the invalidation requirements
from 'real-time clients', such as display and camera. This wait-for-safe
logic ensures that the
On 20/09/2019 14:48, Rob Herring wrote:
Convert the Arm SMMv3 binding to the DT schema format.
Cc: Joerg Roedel
Cc: Mark Rutland
Cc: Will Deacon
Cc: Robin Murphy
Cc: iommu@lists.linux-foundation.org
Signed-off-by: Rob Herring
---
.../devicetree/bindings/iommu/arm,smmu-v3.txt | 77
On Wed, Sep 18, 2019 at 04:26:31PM -0700, Jacob Pan wrote:
> From: Yi L Liu
>
> In any virtualization use case, when the first translation stage
> is "owned" by the guest OS, the host IOMMU driver has no knowledge
> of caching structure updates unless the guest invalidation activities
> are
On Thu, 19 Sep 2019 16:55:57 -0400
Matthew Rosato wrote:
> On 9/19/19 11:20 AM, Cornelia Huck wrote:
> > On Fri, 6 Sep 2019 20:13:50 -0400
> > Matthew Rosato wrote:
> >
> >> From: Pierre Morel
> >>
> >> We define a new device region in vfio.h to be able to
> >> get the ZPCI CLP information
On Thu, 19 Sep 2019 16:57:10 -0400
Matthew Rosato wrote:
> On 9/19/19 11:25 AM, Cornelia Huck wrote:
> > On Fri, 6 Sep 2019 20:13:51 -0400
> > Matthew Rosato wrote:
> >
> >> From: Pierre Morel
> >>
> >> We define a new configuration entry for VFIO/PCI, VFIO_PCI_ZDEV
> >>
> >> When the
On 9/20/19 10:26 AM, Cornelia Huck wrote:
> On Thu, 19 Sep 2019 16:57:10 -0400
> Matthew Rosato wrote:
>
>> On 9/19/19 11:25 AM, Cornelia Huck wrote:
>>> On Fri, 6 Sep 2019 20:13:51 -0400
>>> Matthew Rosato wrote:
>>>
From: Pierre Morel
We define a new configuration entry
On 9/19/19 6:57 PM, Alex Williamson wrote:
> On Fri, 6 Sep 2019 20:13:51 -0400
> Matthew Rosato wrote:
>
>> From: Pierre Morel
>>
>> We define a new configuration entry for VFIO/PCI, VFIO_PCI_ZDEV
>>
>> When the VFIO_PCI_ZDEV feature is configured we initialize
>> a new device region,
On Fri, Sep 20, 2019 at 9:17 AM Robin Murphy wrote:
>
> On 20/09/2019 14:48, Rob Herring wrote:
> > Convert the Arm SMMv3 binding to the DT schema format.
> >
> > Cc: Joerg Roedel
> > Cc: Mark Rutland
> > Cc: Will Deacon
> > Cc: Robin Murphy
> > Cc: iommu@lists.linux-foundation.org
> >
On Wed, Sep 18, 2019 at 04:26:32PM -0700, Jacob Pan wrote:
> From: Jean-Philippe Brucker
>
> Some devices might support multiple DMA address spaces, in particular
> those that have the PCI PASID feature. PASID (Process Address Space ID)
> allows to share process address spaces with devices
Convert the Arm SMMU binding to DT schema.
The existing binding doc doesn't cover the number of variations of
compatible properties found in .dts files. "qcom,msm8998-smmu-v2" was
also missing, so add it.
SoCFPGA Stratix10 has a single clock defined which doesn't match the
binding. This issue
On 9/20/19 10:02 AM, Cornelia Huck wrote:
> On Thu, 19 Sep 2019 16:55:57 -0400
> Matthew Rosato wrote:
>
>> On 9/19/19 11:20 AM, Cornelia Huck wrote:
>>> On Fri, 6 Sep 2019 20:13:50 -0400
>>> Matthew Rosato wrote:
>>>
From: Pierre Morel
We define a new device region in
On Wed, Sep 18, 2019 at 04:26:34PM -0700, Jacob Pan wrote:
> Guest shared virtual address (SVA) may require host to shadow guest
> PASID tables. Guest PASID can also be allocated from the host via
> enlightened interfaces. In this case, guest needs to bind the guest
> mm, i.e. cr3 in guest
Convert the Arm SMMv3 binding to the DT schema format.
Cc: Joerg Roedel
Cc: Mark Rutland
Cc: Will Deacon
Cc: Robin Murphy
Cc: iommu@lists.linux-foundation.org
Signed-off-by: Rob Herring
---
.../devicetree/bindings/iommu/arm,smmu-v3.txt | 77 -
On Wed, Sep 18, 2019 at 04:26:33PM -0700, Jacob Pan wrote:
> +/*
> + * struct ioasid_allocator_data - Internal data structure to hold information
> + * about an allocator. There are two types of allocators:
> + *
> + * - Default allocator always has its own XArray to track the IOASIDs
>
On 9/19/19 6:49 PM, Alex Williamson wrote:
> On Thu, 19 Sep 2019 16:27:08 -0600
> Alex Williamson wrote:
>
>> On Thu, 19 Sep 2019 16:55:57 -0400
>> Matthew Rosato wrote:
>>
>>> On 9/19/19 11:20 AM, Cornelia Huck wrote:
On Fri, 6 Sep 2019 20:13:50 -0400
Matthew Rosato wrote:
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