Hi Rob,
On 1/13/20 3:39 PM, Rob Herring wrote:
> Arm SMMUv3.2 adds support for TLB range invalidate operations.
> Support for range invalidate is determined by the RIL bit in the IDR3
> register.
>
> The range invalidate is in units of the leaf page size and operates on
> 1-32 chunks of a power
On Tue, Jan 14, 2020 at 03:04:36PM +, Will Deacon wrote:
> On Thu, Dec 19, 2019 at 05:30:30PM +0100, Jean-Philippe Brucker wrote:
> > The SMMU can support up to 20 bits of SSID. Add a second level of page
> > tables to accommodate this. Devices that support more than 1024 SSIDs now
> > have a
When base address in RHSA structure doesn't match base address in
each DRHD structure, the base address in last DRHD is printed out.
This doesn't make sense when there are multiple DRHD units, fix it
by printing the buggy RHSA's base address.
Signed-off-by: Zhenzhong Duan
Cc: David Woodhouse
On Fri, Jan 10, 2020 at 08:10:28AM +0100, Christian Zigotzky wrote:
> Hi All,
>
> The SCSI cards work again. [1, 2]
>
> Sorry for bothering you.
No problem, and sorry for not following up earlier. The Christmas
holiday and catch up phase led to a lot of delay.
Thanks a lot for taking care of
On 14/01/2020 20.19, Robin Murphy wrote:
> On 14/01/2020 4:43 pm, Peter Ujfalusi wrote:
>> The dma_pfn_offset should only be applied to an address which is
>> within the
>> dma-ranges range. Any address outside should have offset as 0.
>
> No, that's wrong. If a non-empty dma-ranges is present,
On Wed, Jan 15, 2020 at 07:18:34PM +0800, zhangfei wrote:
> Hi, Greg
>
> On 2020/1/14 下午10:59, Greg Kroah-Hartman wrote:
> > On Mon, Jan 13, 2020 at 11:34:55AM +0800, zhangfei wrote:
> > > Hi, Greg
> > >
> > > Thanks for the review.
> > >
> > > On 2020/1/12 上午3:40, Greg Kroah-Hartman wrote:
> >
Uacce (Unified/User-space-access-intended Accelerator Framework) targets to
provide Shared Virtual Addressing (SVA) between accelerators and processes.
So accelerator can access any data structure of the main cpu.
This differs from the data sharing between cpu and io device, which share
data
On 2020/1/15 下午8:02, Greg Kroah-Hartman wrote:
On Wed, Jan 15, 2020 at 07:18:34PM +0800, zhangfei wrote:
Hi, Greg
On 2020/1/14 下午10:59, Greg Kroah-Hartman wrote:
On Mon, Jan 13, 2020 at 11:34:55AM +0800, zhangfei wrote:
Hi, Greg
Thanks for the review.
On 2020/1/12 上午3:40, Greg
From: Kenneth Lee
Uacce (Unified/User-space-access-intended Accelerator Framework) is
a kernel module targets to provide Shared Virtual Addressing (SVA)
between the accelerator and process.
This patch add document to explain how it works.
Reviewed-by: Jonathan Cameron
Signed-off-by: Kenneth
Hi, Greg
On 2020/1/14 下午10:59, Greg Kroah-Hartman wrote:
On Mon, Jan 13, 2020 at 11:34:55AM +0800, zhangfei wrote:
Hi, Greg
Thanks for the review.
On 2020/1/12 上午3:40, Greg Kroah-Hartman wrote:
On Sat, Jan 11, 2020 at 10:48:37AM +0800, Zhangfei Gao wrote:
+static int uacce_fops_open(struct
On Wed, Jan 15, 2020 at 3:21 AM Auger Eric wrote:
>
> Hi Rob,
>
> On 1/13/20 3:39 PM, Rob Herring wrote:
> > Arm SMMUv3.2 adds support for TLB range invalidate operations.
> > Support for range invalidate is determined by the RIL bit in the IDR3
> > register.
> >
> > The range invalidate is in
Now that we support substream IDs, initialize s1cdmax with the number of
SSID bits supported by a master and the SMMU.
Context descriptor tables are allocated once for the first master
attached to a domain. Therefore attaching multiple devices with
different SSID sizes is tricky, and we currently
Since v4 [1] I addressed some of Will's comment.
Still missing and will be submitted as follow-up patches:
* write STE.V with WRITE_ONCE() (patch 7)
* batch submission of CD invalidation (patch 7)
* Remove WARN_ON_ONCE() in add_device() (patch 13)
Pending Robin's input.
So I think patches 1-10
When adding SSID support to the SMMUv3 driver, we'll need to manipulate
leaf pasid tables and context descriptors. Extract the context
descriptor structure and align with the way stream tables are handled.
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/arm-smmu-v3.c | 46
The SMMU can support up to 20 bits of SSID. Add a second level of page
tables to accommodate this. Devices that support more than 1024 SSIDs now
have a table of 1024 L1 entries (8kB), pointing to tables of 1024 context
descriptors (64kB), allocated on demand.
Signed-off-by: Jean-Philippe Brucker
The SMMUv3 driver, which may be built without CONFIG_PCI, will soon gain
PASID support. Partially revert commit c6e9aefbf9db ("PCI/ATS: Remove
unused PRI and PASID stubs") to re-introduce the PASID stubs, and avoid
adding more #ifdefs to the SMMU driver.
Acked-by: Bjorn Helgaas
Reviewed-by:
Enable PASID for PCI devices that support it. Initialize PASID early in
add_device() because it must be enabled before ATS.
Tested-by: Zhangfei Gao
Reviewed-by: Jonathan Cameron
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/arm-smmu-v3.c | 62 -
1
Support for SSID will require allocating context descriptor tables. Move
the context descriptor allocation to separate functions.
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/arm-smmu-v3.c | 47 +++--
1 file changed, 34 insertions(+), 13 deletions(-)
At the moment, the SMMUv3 driver implements only one stage-1 or stage-2
page directory per device. However SMMUv3 allows more than one address
space for some devices, by providing multiple stage-1 page directories. In
addition to the Stream ID (SID), that identifies a device, we can now have
Since commit 518a2f1925c3 ("dma-mapping: zero memory returned from
dma_alloc_*"), dma_alloc_* always initializes memory to zero, so there
is no need to use dma_zalloc_* or pass the __GFP_ZERO flag anymore.
The flag was introduced by commit 04fa26c71be5 ("iommu/arm-smmu: Convert
DMA buffer
For platform devices that support SubstreamID (SSID), firmware provides
the number of supported SSID bits. Restrict it to what the SMMU supports
and cache it into master->ssid_bits, which will also be used for PCI
PASID.
Reviewed-by: Eric Auger
Reviewed-by: Jonathan Cameron
Signed-off-by:
Let add_device() clean up after itself. The iommu_bus_init() function
does call remove_device() on error, but other sites (e.g. of_iommu) do
not.
Don't free level-2 stream tables because we'd have to track if we
allocated each of them or if they are used by other endpoints. It's not
worth the
Second-level context descriptor tables will be allocated lazily in
arm_smmu_write_ctx_desc(). Help with handling allocation failure by
moving the CD write into arm_smmu_domain_finalise_s1().
Reviewed-by: Eric Auger
Reviewed-by: Jonathan Cameron
Signed-off-by: Jean-Philippe Brucker
---
Named component nodes in the IORT tables describe the number of
Substream ID bits (aka. PASID) supported by the device. Propagate this
value to the fwspec structure in order to enable PASID for platform
devices.
Acked-by: Hanjun Guo
Reviewed-by: Eric Auger
Reviewed-by: Jonathan Cameron
On Arm systems, some platform devices behind an SMMU may support the PASID
feature, which offers multiple address space. Let the firmware tell us
when a device supports PASID.
Reviewed-by: Eric Auger
Reviewed-by: Jonathan Cameron
Reviewed-by: Rob Herring
Signed-off-by: Jean-Philippe Brucker
On 14/01/2020 3:25 pm, Will Deacon wrote:
On Thu, Dec 19, 2019 at 05:30:31PM +0100, Jean-Philippe Brucker wrote:
Let add_device() clean up after itself. The iommu_bus_init() function
does call remove_device() on error, but other sites (e.g. of_iommu) do
not.
Don't free level-2 stream tables
Hi Rob,
On 1/15/20 3:02 PM, Rob Herring wrote:
> On Wed, Jan 15, 2020 at 3:21 AM Auger Eric wrote:
>>
>> Hi Rob,
>>
>> On 1/13/20 3:39 PM, Rob Herring wrote:
>>> Arm SMMUv3.2 adds support for TLB range invalidate operations.
>>> Support for range invalidate is determined by the RIL bit in the
On Wed, Jan 15, 2020 at 01:52:26PM +0100, Jean-Philippe Brucker wrote:
> Since v4 [1] I addressed some of Will's comment.
Thanks! I've tentatively managed to queue all of this apart from the last
patch, since that relies on some pasid symbols being exported from the PCI
core when building the
On Wed, Jan 15, 2020 at 04:42:56PM +, Will Deacon wrote:
> On Wed, Jan 15, 2020 at 01:52:26PM +0100, Jean-Philippe Brucker wrote:
> > Since v4 [1] I addressed some of Will's comment.
>
> Thanks! I've tentatively managed to queue all of this apart from the last
> patch, since that relies on
On Tue, Jan 14, 2020 at 03:25:39PM +, Will Deacon wrote:
> On Thu, Dec 19, 2019 at 05:30:31PM +0100, Jean-Philippe Brucker wrote:
> > Let add_device() clean up after itself. The iommu_bus_init() function
> > does call remove_device() on error, but other sites (e.g. of_iommu) do
> > not.
> >
>
On 1/15/20 4:18 AM, zhangfei wrote:
Hi, Greg
On 2020/1/14 下午10:59, Greg Kroah-Hartman wrote:
On Mon, Jan 13, 2020 at 11:34:55AM +0800, zhangfei wrote:
Hi, Greg
Thanks for the review.
On 2020/1/12 上午3:40, Greg Kroah-Hartman wrote:
On Sat, Jan 11, 2020 at 10:48:37AM +0800, Zhangfei Gao
From: Kenneth Lee
Uacce (Unified/User-space-access-intended Accelerator Framework) targets to
provide Shared Virtual Addressing (SVA) between accelerators and processes.
So accelerator can access any data structure of the main cpu.
This differs from the data sharing between cpu and io device,
Remove the module_param uacce_mode, which is not used currently.
Reviewed-by: Jonathan Cameron
Signed-off-by: Zhangfei Gao
Signed-off-by: Zhou Wang
---
drivers/crypto/hisilicon/zip/zip_main.c | 31 ++-
1 file changed, 6 insertions(+), 25 deletions(-)
diff --git
Register qm to uacce framework for user crypto driver
Reviewed-by: Jonathan Cameron
Signed-off-by: Zhangfei Gao
Signed-off-by: Zhou Wang
---
drivers/crypto/hisilicon/qm.c | 239 +++-
drivers/crypto/hisilicon/qm.h | 11 ++
Address field in device TLB invalidation descriptor is qualified
by the S field. If S field is zero, a single page at page address
specified by address [63:12] is requested to be invalidated. If S
field is set, the least significant bit in the address field with
value 0b (say bit N) indicates the
Hi, Dave
On 2020/1/16 上午12:43, Dave Jiang wrote:
On 1/15/20 4:18 AM, zhangfei wrote:
Hi, Greg
On 2020/1/14 下午10:59, Greg Kroah-Hartman wrote:
On Mon, Jan 13, 2020 at 11:34:55AM +0800, zhangfei wrote:
Hi, Greg
Thanks for the review.
On 2020/1/12 上午3:40, Greg Kroah-Hartman wrote:
On Sat,
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