[PATCH v5 09/15] iommu/vt-d: Check ownership for PASIDs from user-space

2020-07-12 Thread Liu Yi L
When an IOMMU domain with nesting attribute is used for guest SVA, a system-wide PASID is allocated for binding with the device and the domain. For security reason, we need to check the PASID passsed from user-space. e.g. page table bind/unbind and PASID related cache invalidation. Cc: Kevin Tian

[PATCH v5 05/15] vfio: Add PASID allocation/free support

2020-07-12 Thread Liu Yi L
Shared Virtual Addressing (a.k.a Shared Virtual Memory) allows sharing multiple process virtual address spaces with the device for simplified programming model. PASID is used to tag an virtual address space in DMA requests and to identify the related translation structure in IOMMU. When a

[PATCH v5 07/15] vfio/type1: Add VFIO_IOMMU_PASID_REQUEST (alloc/free)

2020-07-12 Thread Liu Yi L
This patch allows user space to request PASID allocation/free, e.g. when serving the request from the guest. PASIDs that are not freed by userspace are automatically freed when the IOASID set is destroyed when process exits. Cc: Kevin Tian CC: Jacob Pan Cc: Alex Williamson Cc: Eric Auger Cc:

[PATCH v5 04/15] vfio/type1: Report iommu nesting info to userspace

2020-07-12 Thread Liu Yi L
This patch exports iommu nesting capability info to user space through VFIO. User space is expected to check this info for supported uAPIs (e.g. PASID alloc/free, bind page table, and cache invalidation) and the vendor specific format information for first level/stage page table that will be bound

[PATCH v5 00/15] vfio: expose virtual Shared Virtual Addressing to VMs

2020-07-12 Thread Liu Yi L
Shared Virtual Addressing (SVA), a.k.a, Shared Virtual Memory (SVM) on Intel platforms allows address space sharing between device DMA and applications. SVA can reduce programming complexity and enhance security. This VFIO series is intended to expose SVA usage to VMs. i.e. Sharing guest

[PATCH v5 13/15] vfio/pci: Expose PCIe PASID capability to guest

2020-07-12 Thread Liu Yi L
This patch exposes PCIe PASID capability to guest for assigned devices. Existing vfio_pci driver hides it from guest by setting the capability length as 0 in pci_ext_cap_length[]. And this patch only exposes PASID capability for devices which has PCIe PASID extended struture in its configuration

[PATCH v5 10/15] vfio/type1: Support binding guest page tables to PASID

2020-07-12 Thread Liu Yi L
Nesting translation allows two-levels/stages page tables, with 1st level for guest translations (e.g. GVA->GPA), 2nd level for host translations (e.g. GPA->HPA). This patch adds interface for binding guest page tables to a PASID. This PASID must have been allocated to user space before the binding

[PATCH v5 02/15] iommu: Report domain nesting info

2020-07-12 Thread Liu Yi L
IOMMUs that support nesting translation needs report the capability info to userspace, e.g. the format of first level/stage paging structures. This patch reports nesting info by DOMAIN_ATTR_NESTING. Caller can get nesting info after setting DOMAIN_ATTR_NESTING. Cc: Kevin Tian CC: Jacob Pan Cc:

[PATCH v5 14/15] vfio: Document dual stage control

2020-07-12 Thread Liu Yi L
From: Eric Auger The VFIO API was enhanced to support nested stage control: a bunch of new iotcls and usage guideline. Let's document the process to follow to set up nested mode. Cc: Kevin Tian CC: Jacob Pan Cc: Alex Williamson Cc: Eric Auger Cc: Jean-Philippe Brucker Cc: Joerg Roedel

[PATCH v5 03/15] iommu/smmu: Report empty domain nesting info

2020-07-12 Thread Liu Yi L
This patch is added as instead of returning a boolean for DOMAIN_ATTR_NESTING, iommu_domain_get_attr() should return an iommu_nesting_info handle. Cc: Will Deacon Cc: Robin Murphy Cc: Eric Auger Cc: Jean-Philippe Brucker Suggested-by: Jean-Philippe Brucker Signed-off-by: Liu Yi L

[PATCH v5 06/15] iommu/vt-d: Support setting ioasid set to domain

2020-07-12 Thread Liu Yi L
>From IOMMU p.o.v., PASIDs allocated and managed by external components (e.g. VFIO) will be passed in for gpasid_bind/unbind operation. IOMMU needs some knowledge to check the PASID ownership, hence add an interface for those components to tell the PASID owner. In latest kernel design, PASID

[PATCH v5 12/15] vfio/type1: Add vSVA support for IOMMU-backed mdevs

2020-07-12 Thread Liu Yi L
Recent years, mediated device pass-through framework (e.g. vfio-mdev) is used to achieve flexible device sharing across domains (e.g. VMs). Also there are hardware assisted mediated pass-through solutions from platform vendors. e.g. Intel VT-d scalable mode which supports Intel Scalable I/O

[PATCH v5 15/15] iommu/vt-d: Support reporting nesting capability info

2020-07-12 Thread Liu Yi L
Cc: Kevin Tian CC: Jacob Pan Cc: Alex Williamson Cc: Eric Auger Cc: Jean-Philippe Brucker Cc: Joerg Roedel Cc: Lu Baolu Signed-off-by: Liu Yi L Signed-off-by: Jacob Pan --- v2 -> v3: *) remove cap/ecap_mask in iommu_nesting_info. --- drivers/iommu/intel/iommu.c | 81

[PATCH v5 08/15] iommu: Pass domain to sva_unbind_gpasid()

2020-07-12 Thread Liu Yi L
From: Yi Sun Current interface is good enough for SVA virtualization on an assigned physical PCI device, but when it comes to mediated devices, a physical device may attached with multiple aux-domains. Also, for guest unbind, the PASID to be unbind should be allocated to the VM. This check

[PATCH v5 01/15] vfio/type1: Refactor vfio_iommu_type1_ioctl()

2020-07-12 Thread Liu Yi L
This patch refactors the vfio_iommu_type1_ioctl() to use switch instead of if-else, and each command got a helper function. Cc: Kevin Tian CC: Jacob Pan Cc: Alex Williamson Cc: Eric Auger Cc: Jean-Philippe Brucker Cc: Joerg Roedel Cc: Lu Baolu Reviewed-by: Eric Auger Suggested-by:

[PATCH v5 11/15] vfio/type1: Allow invalidating first-level/stage IOMMU cache

2020-07-12 Thread Liu Yi L
This patch provides an interface allowing the userspace to invalidate IOMMU cache for first-level page table. It is required when the first level IOMMU page table is not managed by the host kernel in the nested translation setup. Cc: Kevin Tian CC: Jacob Pan Cc: Alex Williamson Cc: Eric Auger

Re: [PATCH v2 3/5] irqchip: Allow QCOM_PDC to be loadable as a permanent module

2020-07-12 Thread Marc Zyngier
On Sat, 11 Jul 2020 00:27:45 +0100, Stephen Boyd wrote: > > Quoting John Stultz (2020-07-10 15:44:18) > > On Thu, Jul 9, 2020 at 11:02 PM Stephen Boyd wrote: > > > > > > Does it work? I haven't looked in detail but I worry that the child > > > irqdomain (i.e. pinctrl-msm) would need to delay

Re: [PATCH 01/21] dt-binding: memory: mediatek: Add a common larb-port header file

2020-07-12 Thread Matthias Brugger
On 11/07/2020 08:48, Yong Wu wrote: Put all the macros about smi larb/port togethers, this is a preparing patch for extending LARB_NR and adding new dom-id support. Signed-off-by: Yong Wu --- include/dt-bindings/memory/mt2712-larb-port.h | 2 +-

Re: [PATCH 06/21] iommu/io-pgtable-arm-v7s: Use ias to check the valid iova in unmap

2020-07-12 Thread Nicolas Boichat
On Sat, Jul 11, 2020 at 2:50 PM Yong Wu wrote: > > As title. > > Signed-off-by: Yong Wu > --- > drivers/iommu/io-pgtable-arm-v7s.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c > b/drivers/iommu/io-pgtable-arm-v7s.c > index

RE: [PATCH v3 0/2] make dma_alloc_coherent NUMA-aware by per-NUMA CMA

2020-07-12 Thread Song Bao Hua (Barry Song)
> -Original Message- > From: Song Bao Hua (Barry Song) > Sent: Sunday, June 28, 2020 11:13 PM > To: h...@lst.de; m.szyprow...@samsung.com; robin.mur...@arm.com; > w...@kernel.org; ganapatrao.kulka...@cavium.com; > catalin.mari...@arm.com > Cc: iommu@lists.linux-foundation.org; Linuxarm

RE: [PATCH] xen: introduce xen_vring_use_dma

2020-07-12 Thread Peng Fan
> Subject: Re: [PATCH] xen: introduce xen_vring_use_dma > > Sorry for the late reply -- a couple of conferences kept me busy. > > > On Wed, 1 Jul 2020, Michael S. Tsirkin wrote: > > On Wed, Jul 01, 2020 at 10:34:53AM -0700, Stefano Stabellini wrote: > > > Would you be in favor of a more

Re: [PATCH 4/5] dma-mapping: add a dma_ops_bypass flag to struct device

2020-07-12 Thread Alexey Kardashevskiy
On 09/07/2020 01:24, Christoph Hellwig wrote: > Several IOMMU drivers have a bypass mode where they can use a direct > mapping if the devices DMA mask is large enough. Add generic support > to the core dma-mapping code to do that to switch those drivers to > a common solution. > >

Re: [PATCH 04/21] dt-binding: mediatek: Add binding for mt8192 IOMMU and SMI

2020-07-12 Thread Pi-Hsun Shih
On Sat, Jul 11, 2020 at 2:50 PM Yong Wu wrote: > > This patch adds decriptions for mt8192 IOMMU and SMI. > > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation > table format. The M4U-SMI HW diagram is as below: > > EMI >

Re: [PATCH 01/21] dt-binding: memory: mediatek: Add a common larb-port header file

2020-07-12 Thread Pi-Hsun Shih
On Mon, Jul 13, 2020 at 2:06 AM Matthias Brugger wrote: > > > > On 11/07/2020 08:48, Yong Wu wrote: > > Put all the macros about smi larb/port togethers, this is a preparing > > patch for extending LARB_NR and adding new dom-id support. > > > > Signed-off-by: Yong Wu > > --- > >