Re: [PATCH 12/21] iommu/mediatek: Add iova reserved function

2020-07-13 Thread Pi-Hsun Shih
On Sat, Jul 11, 2020 at 2:51 PM Yong Wu wrote: > > For multiple iommu_domains, we need to reserve some iova regions, so we > will add mtk_iommu_iova_region structure. It includes the base address > and size of the range. > This is a preparing patch for supporting multi-domain. > > Signed-off-by:

Re: [PATCH 0/4] Bounced DMA support

2020-07-13 Thread Robin Murphy
On 2020-07-13 10:12, Claire Chang wrote: This series implements mitigations for lack of DMA access control on systems without an IOMMU, which could result in the DMA accessing the system memory at unexpected times and/or unexpected addresses, possibly leading to data leakage or corruption. For

[PATCH 1/4] dma-mapping: Add bounced DMA ops

2020-07-13 Thread Claire Chang
The bounced DMA ops provide an implementation of DMA ops that bounce streaming DMA in and out of a specially allocated region. Only the operations relevant to streaming DMA are supported. Signed-off-by: Claire Chang --- include/linux/device.h | 3 + include/linux/dma-mapping.h | 1 +

[PATCH 4/4] of: Add plumbing for bounced DMA pool

2020-07-13 Thread Claire Chang
If a device is not behind an IOMMU, we look up the device node and set up the bounced DMA when the bounced-dma property is presented. One can specify two reserved-memory nodes in the device tree. One with shared-dma-pool to handle the coherent DMA buffer allocation, and another one with

[PATCH 3/4] dt-bindings: of: Add plumbing for bounced DMA pool

2020-07-13 Thread Claire Chang
Introduce the new compatible string, bounced-dma-pool, for bounced DMA. One can specify the address and length of the bounced memory region by bounced-dma-pool in the device tree. Signed-off-by: Claire Chang --- .../reserved-memory/reserved-memory.txt | 36 +++ 1 file

[PATCH 2/4] dma-mapping: Add bounced DMA pool

2020-07-13 Thread Claire Chang
Add the initialization function to create bounce buffer pools from matching reserved-memory nodes in the device tree. The bounce buffer pools provide a basic level of protection against the DMA overwriting buffer contents at unexpected times. However, to protect against general data leakage and

Re: [SPAM]Re: [PATCH 01/21] dt-binding: memory: mediatek: Add a common larb-port header file

2020-07-13 Thread Yong Wu
On Sun, 2020-07-12 at 20:06 +0200, Matthias Brugger wrote: > > On 11/07/2020 08:48, Yong Wu wrote: > > Put all the macros about smi larb/port togethers, this is a preparing > > patch for extending LARB_NR and adding new dom-id support. > > > > Signed-off-by: Yong Wu [...] > > diff --git

Re: [PATCH v4 4/4] PCI/ACS: Enable PCI_ACS_TB for untrusted/external-facing devices

2020-07-13 Thread Joerg Roedel
On Sat, Jul 11, 2020 at 09:58:38PM -0500, Bjorn Helgaas wrote: > If BIOS handed off with ATS enabled and we somehow relied on it being > already enabled, something might break if we start disabling ATS. > Just a theoretical possibility, doesn't seem likely to me. I don't think this will be a

Re: [PATCH 04/21] dt-binding: mediatek: Add binding for mt8192 IOMMU and SMI

2020-07-13 Thread Yong Wu
On Mon, 2020-07-13 at 13:36 +0800, Pi-Hsun Shih wrote: > On Sat, Jul 11, 2020 at 2:50 PM Yong Wu wrote: > > > > This patch adds decriptions for mt8192 IOMMU and SMI. > > > > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation > > table format. The M4U-SMI HW diagram is as

[PATCH 0/4] Bounced DMA support

2020-07-13 Thread Claire Chang
This series implements mitigations for lack of DMA access control on systems without an IOMMU, which could result in the DMA accessing the system memory at unexpected times and/or unexpected addresses, possibly leading to data leakage or corruption. For example, we plan to use the PCI-e bus for

[PATCH] iommu/mediatek: Include liunx/dma-mapping.h

2020-07-13 Thread Joerg Roedel
From: Joerg Roedel This fixes a compile error when cross-compiling the driver on x86-32. Signed-off-by: Joerg Roedel --- drivers/iommu/mtk_iommu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index 6ff62452bbf9..122925dbe547 100644

Re: [PATCH 01/21] dt-binding: memory: mediatek: Add a common larb-port header file

2020-07-13 Thread Yong Wu
On Mon, 2020-07-13 at 13:43 +0800, Pi-Hsun Shih wrote: > On Mon, Jul 13, 2020 at 2:06 AM Matthias Brugger > wrote: > > > > > > > > On 11/07/2020 08:48, Yong Wu wrote: > > > Put all the macros about smi larb/port togethers, this is a preparing > > > patch for extending LARB_NR and adding new

Re: [PATCH 06/21] iommu/io-pgtable-arm-v7s: Use ias to check the valid iova in unmap

2020-07-13 Thread Yong Wu
On Mon, 2020-07-13 at 08:38 +0800, Nicolas Boichat wrote: > On Sat, Jul 11, 2020 at 2:50 PM Yong Wu wrote: > > > > As title. > > > > Signed-off-by: Yong Wu > > --- > > drivers/iommu/io-pgtable-arm-v7s.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git

Re: [PATCH 11/21] iommu/mediatek: Add power-domain operation

2020-07-13 Thread Pi-Hsun Shih
On Sat, Jul 11, 2020 at 2:51 PM Yong Wu wrote: > > In the previous SoC, the M4U HW is in the EMI power domain which is > always on. the latest M4U is in the display power domain which may be > turned on/off, thus we have to add pm_runtime interface for it. > > we should enable its power before

[git pull] IOMMU Fixes for Linux v5.8-rc5

2020-07-13 Thread Joerg Roedel
Hi Linus, The following changes since commit 9ebcfadb0610322ac537dd7aa5d9cbc2b2894c68: Linux 5.8-rc3 (2020-06-28 15:00:24 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git tags/iommu-fixes-v5.8-rc5 for you to fetch changes up to

Re: [PATCH v10 4/5] dt-bindings: arm-smmu: add binding for Tegra194 SMMU

2020-07-13 Thread Robin Murphy
On 2020-07-10 21:29, Krishna Reddy wrote: Thanks Rob. One question on setting "minItems: ". Please see below. +allOf: + - if: + properties: +compatible: + contains: +enum: + - nvidia,tegra194-smmu +then: + properties: +reg: +

Re: [PATCH v9 4/7] iommu/arm-smmu: Add a pointer to the attached device to smmu_domain

2020-07-13 Thread Will Deacon
On Fri, Jun 26, 2020 at 02:00:38PM -0600, Jordan Crouse wrote: > Add a link to the pointer to the struct device that is attached to a > domain. This makes it easy to get the pointer if it is needed in the > implementation specific code. > > Signed-off-by: Jordan Crouse > --- > >

Re: [PATCH 1/4] dma-mapping: Add bounced DMA ops

2020-07-13 Thread Robin Murphy
On 2020-07-13 10:12, Claire Chang wrote: The bounced DMA ops provide an implementation of DMA ops that bounce streaming DMA in and out of a specially allocated region. Only the operations relevant to streaming DMA are supported. I think there are too many implicit assumptions here - apparently

Re: [PATCH 2/2] iommu/dma: Avoid SAC address trick for PCIe devices

2020-07-13 Thread Joerg Roedel
On Wed, Jul 08, 2020 at 12:32:42PM +0100, Robin Murphy wrote: > As for the intel-iommu implementation, relegate the opportunistic > attempt to allocate a SAC address to the domain of conventional PCI > devices only, to avoid it increasingly causing far more performance > issues than possible

Re: [PATCH v5 03/15] iommu/smmu: Report empty domain nesting info

2020-07-13 Thread Will Deacon
On Sun, Jul 12, 2020 at 04:20:58AM -0700, Liu Yi L wrote: > This patch is added as instead of returning a boolean for DOMAIN_ATTR_NESTING, > iommu_domain_get_attr() should return an iommu_nesting_info handle. > > Cc: Will Deacon > Cc: Robin Murphy > Cc: Eric Auger > Cc: Jean-Philippe Brucker

Re: [PATCH v6 00/10] MT6779 IOMMU SUPPORT

2020-07-13 Thread Joerg Roedel
On Sat, Jul 11, 2020 at 03:11:33PM +0800, Yong Wu wrote: > The SMI part always go with the IOMMU, Could you also help apply the > mt6779 SMI basical part [1][2]. Both has already got reviewed-by from > Rob and Matthias. and the [3] in that patchset is for performance > improvement, it's not so

Re: [PATCH v8 04/12] arm64: mm: Pin down ASIDs for sharing mm with devices

2020-07-13 Thread Will Deacon
On Thu, Jun 18, 2020 at 05:51:17PM +0200, Jean-Philippe Brucker wrote: > To enable address space sharing with the IOMMU, introduce mm_context_get() > and mm_context_put(), that pin down a context and ensure that it will keep > its ASID after a rollover. Export the symbols to let the modular SMMUv3

Re: [PATCH v10 5/5] iommu/arm-smmu: Add global/context fault implementation hooks

2020-07-13 Thread Will Deacon
On Tue, Jul 07, 2020 at 10:00:17PM -0700, Krishna Reddy wrote: > Add global/context fault hooks to allow vendor specific implementations > override default fault interrupt handlers. > > Update NVIDIA implementation to override the default global/context fault > interrupt handlers and handle

Re: [PATCH v10 0/5] NVIDIA ARM SMMU Implementation

2020-07-13 Thread Will Deacon
On Tue, Jul 07, 2020 at 10:00:12PM -0700, Krishna Reddy wrote: > Changes in v10: > Perform SMMU base ioremap before calling implementation init. > Check for Global faults across both ARM MMU-500s during global interrupt. > Check for context faults across all contexts of both ARM MMU-500s during >

[PATCH -next] iommu: Make some functions static

2020-07-13 Thread Wei Yongjun
The sparse tool complains as follows: drivers/iommu/iommu.c:386:5: warning: symbol 'iommu_insert_resv_region' was not declared. Should it be static? drivers/iommu/iommu.c:2182:5: warning: symbol '__iommu_map' was not declared. Should it be static? Those functions are not used outside of

Re: [PATCH v10 2/5] iommu/arm-smmu: ioremap smmu mmio region before implementation init

2020-07-13 Thread Robin Murphy
On 2020-07-08 06:00, Krishna Reddy wrote: ioremap smmu mmio region before calling into implementation init. This is necessary to allow mapped address available during vendor specific implementation init. Reviewed-by: Robin Murphy Signed-off-by: Krishna Reddy --- drivers/iommu/arm-smmu.c

Re: [PATCH v2] iommu/arm-smmu: Mark qcom_smmu_client_of_match as possibly unused

2020-07-13 Thread Joerg Roedel
On Mon, Jul 13, 2020 at 02:33:26PM +0100, Will Deacon wrote: > I can't see this in Joerg's tree or in linux-next. Joerg: did you pick this > one up? (I thought you did, but I can't find it!). Yes, its in the tree and and will be pushed soon. I'll also send it to Linus today. Joerg

Re: [PATCH v2] iommu/arm-smmu: Mark qcom_smmu_client_of_match as possibly unused

2020-07-13 Thread Will Deacon
On Mon, Jun 08, 2020 at 04:13:08PM +0100, Will Deacon wrote: > On Thu, Jun 04, 2020 at 02:39:04PM -0600, Jordan Crouse wrote: > > When CONFIG_OF=n of_match_device() gets pre-processed out of existence > > leaving qcom-smmu_client_of_match unused. Mark it as possibly unused to > > keep the compiler

Re: [PATCH] iommu/arm-smmu: Add a init_context_bank implementation hook

2020-07-13 Thread Will Deacon
On Thu, Jun 11, 2020 at 04:36:56PM -0600, Jordan Crouse wrote: > Add a new implementation hook to allow the implementation specific code > to tweek the context bank configuration just before it gets written. > The first user will be the Adreno GPU implementation to turn on > SCTLR.HUPCF to ensure

Re: [Freedreno] [PATCH v2 1/6] iommu/arm-smmu: Add auxiliary domain support for arm-smmuv2

2020-07-13 Thread Jordan Crouse
On Tue, Jul 07, 2020 at 08:09:41AM -0700, Rob Clark wrote: > On Tue, Jul 7, 2020 at 5:34 AM Robin Murphy wrote: > > > > On 2020-06-26 21:04, Jordan Crouse wrote: > > > Support auxiliary domains for arm-smmu-v2 to initialize and support > > > multiple pagetables for a single SMMU context bank.

Re: [Freedreno] [PATCH] iommu/arm-smmu: Add a init_context_bank implementation hook

2020-07-13 Thread Jordan Crouse
On Mon, Jul 13, 2020 at 08:03:32PM +0100, Will Deacon wrote: > On Mon, Jul 13, 2020 at 11:00:32AM -0600, Jordan Crouse wrote: > > On Mon, Jul 13, 2020 at 04:11:23PM +0100, Will Deacon wrote: > > > On Thu, Jun 11, 2020 at 04:36:56PM -0600, Jordan Crouse wrote: > > > > Add a new implementation hook

Re: [Freedreno] [PATCH v9 4/7] iommu/arm-smmu: Add a pointer to the attached device to smmu_domain

2020-07-13 Thread Jordan Crouse
On Mon, Jul 13, 2020 at 04:09:02PM +0100, Will Deacon wrote: > On Fri, Jun 26, 2020 at 02:00:38PM -0600, Jordan Crouse wrote: > > Add a link to the pointer to the struct device that is attached to a > > domain. This makes it easy to get the pointer if it is needed in the > > implementation

Re: [PATCH] iommu/arm-smmu: Add a init_context_bank implementation hook

2020-07-13 Thread Jordan Crouse
On Mon, Jul 13, 2020 at 04:11:23PM +0100, Will Deacon wrote: > On Thu, Jun 11, 2020 at 04:36:56PM -0600, Jordan Crouse wrote: > > Add a new implementation hook to allow the implementation specific code > > to tweek the context bank configuration just before it gets written. > > The first user will

Re: [PATCH] iommu/arm-smmu: Add a init_context_bank implementation hook

2020-07-13 Thread Will Deacon
On Mon, Jul 13, 2020 at 11:00:32AM -0600, Jordan Crouse wrote: > On Mon, Jul 13, 2020 at 04:11:23PM +0100, Will Deacon wrote: > > On Thu, Jun 11, 2020 at 04:36:56PM -0600, Jordan Crouse wrote: > > > Add a new implementation hook to allow the implementation specific code > > > to tweek the context

[PATCH 0/9] R8A774E1 SoC enable support for IPMMU, DMAC, GPIO and AVB

2020-07-13 Thread Lad Prabhakar
Hi All, This patch series adds device nodes for IPMMU, DMAC, GPIO and AVB nodes for RZ/G2H (R8A774E1) SoC. Cheers, Prabhakar Lad Prabhakar (3): dt-bindings: iommu: renesas,ipmmu-vmsa: Add r8a774e1 support dt-bindings: dma: renesas,rcar-dmac: Document R8A774E1 bindings dt-bindings: gpio:

[PATCH 1/9] dt-bindings: iommu: renesas, ipmmu-vmsa: Add r8a774e1 support

2020-07-13 Thread Lad Prabhakar
Document RZ/G2H (R8A774E1) SoC bindings. Signed-off-by: Lad Prabhakar --- Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml

[PATCH 9/9] arm64: dts: renesas: r8a774e1: Add Ethernet AVB node

2020-07-13 Thread Lad Prabhakar
From: Marian-Cristian Rotariu This patch adds the SoC specific part of the Ethernet AVB device tree node. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 41 +-- 1 file changed, 39 insertions(+), 2

[PATCH 7/9] arm64: dts: renesas: r8a774e1: Add GPIO device nodes

2020-07-13 Thread Lad Prabhakar
From: Marian-Cristian Rotariu Add GPIO device nodes to the DT of the r8a774e1 SoC. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 73 +-- 1 file changed, 56 insertions(+), 17 deletions(-) diff --git

[PATCH 5/9] arm64: dts: renesas: r8a774e1: Add SYS-DMAC device nodes

2020-07-13 Thread Lad Prabhakar
From: Marian-Cristian Rotariu Add sys-dmac[0-2] device nodes for RZ/G2H (R8A774E1) SoC. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 126 ++ 1 file changed, 126 insertions(+) diff --git

[PATCH 6/9] dt-bindings: gpio: renesas, rcar-gpio: Add r8a774e1 support

2020-07-13 Thread Lad Prabhakar
Document Renesas RZ/G2H (R8A774E1) GPIO blocks compatibility within the relevant dt-bindings. Signed-off-by: Lad Prabhakar --- Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml | 1 + 1 file changed, 1 insertion(+) diff --git

[PATCH 8/9] dt-bindings: net: renesas, ravb: Add support for r8a774e1 SoC

2020-07-13 Thread Lad Prabhakar
From: Marian-Cristian Rotariu Document RZ/G2H (R8A774E1) SoC bindings. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar --- Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 + 1 file changed, 1 insertion(+) diff --git

[PATCH 3/9] arm64: dts: renesas: r8a774e1: Add IPMMU device nodes

2020-07-13 Thread Lad Prabhakar
From: Marian-Cristian Rotariu Add RZ/G2H (R8A774E1) IPMMU nodes. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 121 ++ 1 file changed, 121 insertions(+) diff --git

[PATCH 2/9] iommu/ipmmu-vmsa: Hook up R8A774E1 DT matching code

2020-07-13 Thread Lad Prabhakar
From: Marian-Cristian Rotariu Add support for RZ/G2H (R8A774E1) SoC IPMMUs. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar --- drivers/iommu/ipmmu-vmsa.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c

Re: [PATCH v2 5/5] firmware: QCOM_SCM: Allow qcom_scm driver to be loadable as a permenent module

2020-07-13 Thread Will Deacon
On Fri, Jul 10, 2020 at 03:21:53PM -0700, John Stultz wrote: > On Fri, Jul 10, 2020 at 12:54 AM Will Deacon wrote: > > On Thu, Jul 09, 2020 at 08:28:45PM -0700, John Stultz wrote: > > > On Thu, Jul 2, 2020 at 7:18 AM Will Deacon wrote: > > > > On Thu, Jun 25, 2020 at 12:10:39AM +, John

Re: [PATCH v2 5/5] firmware: QCOM_SCM: Allow qcom_scm driver to be loadable as a permenent module

2020-07-13 Thread John Stultz
On Mon, Jul 13, 2020 at 1:41 PM Will Deacon wrote: > > On Fri, Jul 10, 2020 at 03:21:53PM -0700, John Stultz wrote: > > On Fri, Jul 10, 2020 at 12:54 AM Will Deacon wrote: > > > On Thu, Jul 09, 2020 at 08:28:45PM -0700, John Stultz wrote: > > > > On Thu, Jul 2, 2020 at 7:18 AM Will Deacon

Re: [PATCH v2 06/12] of/iommu: Make of_map_rid() PCI agnostic

2020-07-13 Thread Rob Herring
On Fri, 19 Jun 2020 09:20:07 +0100, Lorenzo Pieralisi wrote: > There is nothing PCI specific (other than the RID - requester ID) > in the of_map_rid() implementation, so the same function can be > reused for input/output IDs mapping for other busses just as well. > > Rename the RID

Re: [PATCH v7 08/36] drm: exynos: fix common struct sg_table related issues

2020-07-13 Thread Inki Dae
20. 6. 19. 오후 7:36에 Marek Szyprowski 이(가) 쓴 글: > The Documentation/DMA-API-HOWTO.txt states that the dma_map_sg() function > returns the number of the created entries in the DMA address space. > However the subsequent calls to the dma_sync_sg_for_{device,cpu}() and > dma_unmap_sg must be called

[iommu:core 18/19] drivers/iommu/exynos-iommu.c:724:20: error: conflicting types for 'update_pte'

2020-07-13 Thread kernel test robot
Hi Robin, First bad commit (maybe != root cause): tree: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git core head: 97215a7df4351fdd9141418568be872fb1032d6e commit: b4ceb4a5359ed1c9ba4a20acf3a70d4bbead3248 [18/19] iommu: Tidy up Kconfig for SoC IOMMUs config:

[RFC PATCH] iommu/arm-smmu: arm_smmu_setup_identity() can be static

2020-07-13 Thread kernel test robot
Signed-off-by: kernel test robot --- arm-smmu.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 2e27cf9815ab6..fb85e716ae9ac 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1924,7 +1924,7

Re: [PATCH 1/5] iommu/arm-smmu: Make all valid stream mappings BYPASS

2020-07-13 Thread kernel test robot
Hi Bjorn, I love your patch! Perhaps something to improve: [auto build test WARNING on iommu/next] [also build test WARNING on arm-perf/for-next/perf v5.8-rc5 next-20200713] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use

Re: [PATCH v4 1/5] docs: IOMMU user API

2020-07-13 Thread Alex Williamson
On Tue, 7 Jul 2020 16:43:45 -0700 Jacob Pan wrote: > IOMMU UAPI is newly introduced to support communications between guest > virtual IOMMU and host IOMMU. There has been lots of discussions on how > it should work with VFIO UAPI and userspace in general. > > This document is indended to

Re: [PATCH v8 07/12] iommu/arm-smmu-v3: Share process page tables

2020-07-13 Thread Will Deacon
On Thu, Jun 18, 2020 at 05:51:20PM +0200, Jean-Philippe Brucker wrote: > With Shared Virtual Addressing (SVA), we need to mirror CPU TTBR, TCR, > MAIR and ASIDs in SMMU contexts. Each SMMU has a single ASID space split > into two sets, shared and private. Shared ASIDs correspond to those >

Re: [PATCH] iommu/mediatek: Include liunx/dma-mapping.h

2020-07-13 Thread Matthias Brugger
On 13/07/2020 12:16, Joerg Roedel wrote: From: Joerg Roedel This fixes a compile error when cross-compiling the driver on x86-32. Signed-off-by: Joerg Roedel Reviewed-by: Matthias Brugger --- drivers/iommu/mtk_iommu.h | 1 + 1 file changed, 1 insertion(+) diff --git

Re: [PATCH v3 3/4] dt-bindings: arm-smmu: add compatible string for Marvell Armada-AP806 SMMU-500

2020-07-13 Thread Rob Herring
On Fri, Jul 03, 2020 at 11:26:32AM +0200, Tomasz Nowicki wrote: > On 03.07.2020 11:05, Robin Murphy wrote: > > On 2020-07-02 21:16, Tomasz Nowicki wrote: > > > Add specific compatible string for Marvell usage due to errata of > > > accessing 64bits registers of ARM SMMU, in AP806. > > > > > >

[PATCH 4/9] dt-bindings: dma: renesas, rcar-dmac: Document R8A774E1 bindings

2020-07-13 Thread Lad Prabhakar
Renesas RZ/G2H (R8A774E1) SoC also has the R-Car gen3 compatible DMA controllers, therefore document RZ/G2H specific bindings. Signed-off-by: Lad Prabhakar --- Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml | 1 + 1 file changed, 1 insertion(+) diff --git

[PATCH v6 02/12] iommu/vt-d: Change flags type to unsigned int in binding mm

2020-07-13 Thread Fenghua Yu
"flags" passed to intel_svm_bind_mm() is a bit mask and should be defined as "unsigned int" instead of "int". Change its type to "unsigned int". Suggested-by: Thomas Gleixner Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck Reviewed-by: Lu Baolu --- v5: - Reviewed by Lu Baolu v2: - Add this

[PATCH v6 08/12] fork: Clear PASID for new mm

2020-07-13 Thread Fenghua Yu
When a new mm is created, its PASID should be cleared, i.e. the PASID is initialized to its init state 0 on both ARM and X86. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Add this patch to initialize PASID value for a new mm. include/linux/mm_types.h | 2 ++ kernel/fork.c

[PATCH v6 01/12] iommu: Change type of pasid to u32

2020-07-13 Thread Fenghua Yu
PASID is defined as a few different types in iommu including "int", "u32", and "unsigned int". To be consistent and to match with uapi definitions, define PASID and its variations (e.g. max PASID) as "u32". "u32" is also shorter and a little more explicit than "unsigned int". No PASID type change

[PATCH v6 05/12] x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature

2020-07-13 Thread Fenghua Yu
From: Yu-cheng Yu ENQCMD instruction reads PASID from IA32_PASID MSR. The MSR is stored in the task's supervisor FPU PASID state and is context switched by XSAVES/XRSTORS. Signed-off-by: Yu-cheng Yu Co-developed-by: Fenghua Yu Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: -

[PATCH v6 10/12] x86/mmu: Allocate/free PASID

2020-07-13 Thread Fenghua Yu
A PASID is allocated for an "mm" the first time any thread attaches to an SVM capable device. Later device attachments (whether to the same device or another SVM device) will re-use the same PASID. The PASID is freed when the process exits (so no need to keep reference counts on how many SVM

[PATCH v6 09/12] x86/process: Clear PASID state for a newly forked/cloned thread

2020-07-13 Thread Fenghua Yu
The PASID state has to be cleared on forks, since the child has a different address space. The PASID is also cleared for thread clone. While it would be correct to inherit the PASID in this case, it is unknown whether the new task will use ENQCMD. Giving it the PASID "just in case" would have the

[PATCH v6 03/12] docs: x86: Add documentation for SVA (Shared Virtual Addressing)

2020-07-13 Thread Fenghua Yu
From: Ashok Raj ENQCMD and Data Streaming Accelerator (DSA) and all of their associated features are a complicated stack with lots of interconnected pieces. This documentation provides a big picture overview for all of the features. Signed-off-by: Ashok Raj Co-developed-by: Fenghua Yu

[PATCH v6 04/12] x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions

2020-07-13 Thread Fenghua Yu
Work submission instruction comes in two flavors. ENQCMD can be called both in ring 3 and ring 0 and always uses the contents of PASID MSR when shipping the command to the device. ENQCMDS allows a kernel driver to submit commands on behalf of a user process. The driver supplies the PASID value in

[PATCH v6 06/12] x86/msr-index: Define IA32_PASID MSR

2020-07-13 Thread Fenghua Yu
The IA32_PASID MSR (0xd93) contains the Process Address Space Identifier (PASID), a 20-bit value. Bit 31 must be set to indicate the value programmed in the MSR is valid. Hardware uses PASID to identify process address space and direct responses to the right address space. Signed-off-by: Fenghua

[PATCH v6 11/12] sched: Define and initialize a flag to identify valid PASID in the task

2020-07-13 Thread Fenghua Yu
From: Peter Zijlstra The flag is defined for the task to identify if the task has a valid PASID. Its initial value is 0 when the task is forked/cloned. It will be used shortly. Signed-off-by: Peter Zijlstra Co-developed-by: Fenghua Yu Signed-off-by: Fenghua Yu --- v2: - Add this patch to

[PATCH v6 12/12] x86/traps: Fix up invalid PASID

2020-07-13 Thread Fenghua Yu
A #GP fault is generated when ENQCMD instruction is executed without a valid PASID value programmed in the current thread's PASID MSR. The #GP fault handler will initialize the MSR if a PASID has been allocated for this process. Decoding the user instruction is ugly and sets a bad architecture

[PATCH v6 00/12] x86: tag application address space for devices

2020-07-13 Thread Fenghua Yu
Hi, Thomas, Joerg, and other maintainers, This series only has one change in patch 1 on top of v5 (see change log). Could you please consider to merge it upstream? Thanks. -Fenghua = Typical hardware devices require a driver stack to translate application buffers to hardware addresses,

[PATCH v6 07/12] mm: Define pasid in mm

2020-07-13 Thread Fenghua Yu
PASID is shared by all threads in a process. So the logical place to keep track of it is in the "mm". Both ARM and X86 need to use the PASID in the "mm". Suggested-by: Christoph Hellwig Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v4: - Change PASID type to u32 (Christoph) v3: -

Re: [PATCH v7 07/36] drm: exynos: use common helper for a scatterlist contiguity check

2020-07-13 Thread Inki Dae
20. 6. 19. 오후 7:36에 Marek Szyprowski 이(가) 쓴 글: > Use common helper for checking the contiguity of the imported dma-buf. > > Signed-off-by: Marek Szyprowski Acked-by : Inki Dae Thanks, Inki Dae > --- > drivers/gpu/drm/exynos/exynos_drm_gem.c | 23 +++ > 1 file changed,

Re: [git pull] IOMMU Fixes for Linux v5.8-rc5

2020-07-13 Thread pr-tracker-bot
The pull request you sent on Mon, 13 Jul 2020 17:36:54 +0200: > git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git > tags/iommu-fixes-v5.8-rc5 has been merged into torvalds/linux.git: https://git.kernel.org/torvalds/c/0dc589da873b58b70f4caf4b070fb0cf70fdd1dc Thank you! --

RE: [PATCH v6 03/12] docs: x86: Add documentation for SVA (Shared Virtual Addressing)

2020-07-13 Thread Liu, Yi L
> From: Fenghua Yu > Sent: Tuesday, July 14, 2020 7:48 AM > > From: Ashok Raj > > ENQCMD and Data Streaming Accelerator (DSA) and all of their associated > features > are a complicated stack with lots of interconnected pieces. > This documentation provides a big picture overview for all of

Re: [Freedreno] [PATCH] iommu/arm-smmu: Add a init_context_bank implementation hook

2020-07-13 Thread Sai Prakash Ranjan
On 2020-07-14 00:43, Jordan Crouse wrote: On Mon, Jul 13, 2020 at 08:03:32PM +0100, Will Deacon wrote: On Mon, Jul 13, 2020 at 11:00:32AM -0600, Jordan Crouse wrote: > On Mon, Jul 13, 2020 at 04:11:23PM +0100, Will Deacon wrote: > > On Thu, Jun 11, 2020 at 04:36:56PM -0600, Jordan Crouse wrote:

RE: [PATCH v6 01/12] iommu: Change type of pasid to u32

2020-07-13 Thread Liu, Yi L
> From: Fenghua Yu > Sent: Tuesday, July 14, 2020 7:48 AM > > PASID is defined as a few different types in iommu including "int", > "u32", and "unsigned int". To be consistent and to match with uapi > definitions, define PASID and its variations (e.g. max PASID) as "u32". > "u32" is also shorter

Re: [PATCH v4 1/5] docs: IOMMU user API

2020-07-13 Thread Jacob Pan
Hi Alex, On Mon, 13 Jul 2020 16:48:42 -0600 Alex Williamson wrote: > On Tue, 7 Jul 2020 16:43:45 -0700 > Jacob Pan wrote: > > > IOMMU UAPI is newly introduced to support communications between > > guest virtual IOMMU and host IOMMU. There has been lots of > > discussions on how it should