[PATCH v2] MAINTAINERS: update QUALCOMM IOMMU after Arm SMMU drivers move

2020-08-24 Thread Lukas Bulwahn
Commit e86d1aa8b60f ("iommu/arm-smmu: Move Arm SMMU drivers into their own subdirectory") moved drivers/iommu/qcom_iommu.c to drivers/iommu/arm/arm-smmu/qcom_iommu.c amongst other moves, adjusted some sections in MAINTAINERS, but missed adjusting the QUALCOMM IOMMU section. Hence,

Re: [patch RFC 26/38] x86/xen: Wrap XEN MSI management into irqdomain

2020-08-24 Thread Jürgen Groß
On 21.08.20 02:24, Thomas Gleixner wrote: To allow utilizing the irq domain pointer in struct device it is necessary to make XEN/MSI irq domain compatible. While the right solution would be to truly convert XEN to irq domains, this is an exercise which is not possible for mere mortals with

Re: [PATCH v4 07/15] iommu/vt-d: Delegate the dma domain to upper layer

2020-08-24 Thread Chris Wilson
Quoting Lu Baolu (2020-08-24 07:31:23) > Hi Chris, > > On 2020/8/22 2:33, Chris Wilson wrote: > > Quoting Lu Baolu (2019-05-25 06:41:28) > >> This allows the iommu generic layer to allocate a dma domain and > >> attach it to a device through the iommu api's. With all types of > >> domains being

Re: Where are iommu region setup in dma_alloc_from_dev_coherent() track?

2020-08-24 Thread Robin Murphy
On 2020-08-24 08:01, Сергей Пыптев wrote: Hi! I try to port our 3D scanner driver to kernel v4.9 and I have a trouble. I can not find a correct way to allocate DMA memory with correct iommu setup. Could you help me? HW: Tegra X1 and Tegra X2 (arm64), our PCIe bus master device uses about

Re: [PATCH] iommu/vt-d:Add support for probing ACPI device in RMRR

2020-08-24 Thread Dan Carpenter
Hi FelixCuioc, Thank you for the patch! Perhaps something to improve: url: https://github.com/0day-ci/linux/commits/FelixCuioc/iommu-vt-d-Add-support-for-probing-ACPI-device-in-RMRR/20200818-104920 base: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next config:

Re: [PATCH v4 07/15] iommu/vt-d: Delegate the dma domain to upper layer

2020-08-24 Thread Lu Baolu
Hi Chris, On 2020/8/22 2:33, Chris Wilson wrote: Quoting Lu Baolu (2019-05-25 06:41:28) This allows the iommu generic layer to allocate a dma domain and attach it to a device through the iommu api's. With all types of domains being delegated to upper layer, we can remove an internal flag which

Where are iommu region setup in dma_alloc_from_dev_coherent() track?

2020-08-24 Thread Сергей Пыптев
Hi! I try to port our 3D scanner driver to kernel v4.9 and I have a trouble. I can not find a correct way to allocate DMA memory with correct iommu setup. Could you help me? HW: Tegra X1 and Tegra X2 (arm64), our PCIe bus master device uses about 200M of system memory to send data from

Re: [PATCH v2 1/9] docs: Document IO Address Space ID (IOASID) APIs

2020-08-24 Thread Jean-Philippe Brucker
On Fri, Aug 21, 2020 at 09:35:10PM -0700, Jacob Pan wrote: > IOASID is used to identify address spaces that can be targeted by device > DMA. It is a system-wide resource that is essential to its many users. > This document is an attempt to help developers from all vendors navigate > the APIs. At

[PATCH 0/2] iommu/amd: Fix IOMMUv2 devices when SME is active

2020-08-24 Thread Joerg Roedel
From: Joerg Roedel Hi, Some IOMMUv2 capable devices do not work correctly when SME is active, because their DMA mask does not include the encryption bit, so that they can not DMA to encrypted memory directly. The IOMMU can jump in here, but the AMD IOMMU driver puts IOMMUv2 capable devices

[PATCH 1/2] iommu/amd: Do not force direct mapping when SME is active

2020-08-24 Thread Joerg Roedel
From: Joerg Roedel Do not force devices supporting IOMMUv2 to be direct mapped when memory encryption is active. This might cause them to be unusable because their DMA mask does not include the encryption bit. Signed-off-by: Joerg Roedel --- drivers/iommu/amd/iommu.c | 7 ++- 1 file

[PATCH 2/2] iommu/amd: Do not use IOMMUv2 functionality when SME is active

2020-08-24 Thread Joerg Roedel
From: Joerg Roedel When memory encryption is active the device is likely not in a direct mapped domain. Forbid using IOMMUv2 functionality for now until finer grained checks for this have been implemented. Signed-off-by: Joerg Roedel --- drivers/iommu/amd/iommu_v2.c | 7 +++ 1 file

Re: [PATCH 16/18] staging/media/tegra-vde: Clean up IOMMU workaround

2020-08-24 Thread Robin Murphy
On 2020-08-23 22:34, Dmitry Osipenko wrote: 21.08.2020 03:11, Robin Murphy пишет: ... Hello, Robin! Thank you for yours work! Some drivers, like this Tegra VDE (Video Decoder Engine) driver for example, do not want to use implicit IOMMU domain. That isn't (intentionally) changing here - the

Re: [PATCH 00/18] Convert arch/arm to use iommu-dma

2020-08-24 Thread Marek Szyprowski
Hi Robin, On 20.08.2020 17:08, Robin Murphy wrote: > Hi all, > > After 5 years or so of intending to get round to this, finally the > time comes! The changes themselves actualy turn out to be relatively > mechanical; the bigger concern appears to be how to get everything > merged across about 5

Re: Is: virtio_gpu_object_shmem_init issues? Was:Re: upstream boot error: general protection fault in swiotlb_map

2020-08-24 Thread Christoph Hellwig
On Mon, Aug 24, 2020 at 11:06:51AM -0400, Konrad Rzeszutek Wilk wrote: > So it fails at > > 683 dev_WARN_ONCE(dev, 1, > > 684 "swiotlb addr %pad+%zu overflow (mask %llx, bus > limit %llx).\n", > 685

[PATCH 04/20] iommu/arm-smmu: Prepare for the adreno-smmu implementation

2020-08-24 Thread Rob Clark
From: Jordan Crouse Do a bit of prep work to add the upcoming adreno-smmu implementation. Add an hook to allow the implementation to choose which context banks to allocate. Move some of the common structs to arm-smmu.h in anticipation of them being used by the implementations and update some

[PATCH 02/20] iommu/arm-smmu: Pass io-pgtable config to implementation specific function

2020-08-24 Thread Rob Clark
From: Jordan Crouse Construct the io-pgtable config before calling the implementation specific init_context function and pass it so the implementation specific function can get a chance to change it before the io-pgtable is created. Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark ---

[PATCH 05/20] iommu: add private interface for adreno-smmu

2020-08-24 Thread Rob Clark
From: Rob Clark This interface will be used for drm/msm to coordinate with the qcom_adreno_smmu_impl to enable/disable TTBR0 translation. Once TTBR0 translation is enabled, the GPU's CP (Command Processor) will directly switch TTBR0 pgtables (and do the necessary TLB inv) synchronized to the

[PATCH 09/20] iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU

2020-08-24 Thread Rob Clark
From: Jordan Crouse Add a special implementation for the SMMU attached to most Adreno GPU target triggered from the qcom,adreno-smmu compatible string. The new Adreno SMMU implementation will enable split pagetables (TTBR1) for the domain attached to the GPU device (SID 0) and hard code it

[PATCH 07/20] drm/msm: set adreno_smmu as gpu's drvdata

2020-08-24 Thread Rob Clark
From: Rob Clark This will be populated by adreno-smmu, to provide a way for coordinating enabling/disabling TTBR0 translation. Signed-off-by: Rob Clark Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/adreno_device.c | 2 -- drivers/gpu/drm/msm/msm_gpu.c | 2 +-

[PATCH 00/20] iommu/arm-smmu + drm/msm: per-process GPU pgtables

2020-08-24 Thread Rob Clark
From: Rob Clark This series adds an Adreno SMMU implementation to arm-smmu to allow GPU hardware pagetable switching. The Adreno GPU has built in capabilities to switch the TTBR0 pagetable during runtime to allow each individual instance or application to have its own pagetable. In order to

[PATCH 11/20] drm/msm: Add a context pointer to the submitqueue

2020-08-24 Thread Rob Clark
From: Jordan Crouse Each submitqueue is attached to a context. Add a pointer to the context to the submitqueue at create time and refcount it so that it stays around through the life of the queue. Co-developed-by: Rob Clark Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark ---

[PATCH 13/20] drm/msm: Set the global virtual address range from the IOMMU domain

2020-08-24 Thread Rob Clark
From: Jordan Crouse Use the aperture settings from the IOMMU domain to set up the virtual address range for the GPU. This allows us to transparently deal with IOMMU side features (like split pagetables). Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark ---

[PATCH 14/20] drm/msm: Add support to create a local pagetable

2020-08-24 Thread Rob Clark
From: Jordan Crouse Add support to create a io-pgtable for use by targets that support per-instance pagetables. In order to support per-instance pagetables the GPU SMMU device needs to have the qcom,adreno-smmu compatible string and split pagetables enabled. Signed-off-by: Jordan Crouse

[PATCH 19/20] iommu/arm-smmu: add a way for implementations to influence SCTLR

2020-08-24 Thread Rob Clark
From: Rob Clark For the Adreno GPU's SMMU, we want SCTLR.HUPCF set to ensure that pending translations are not terminated on iova fault. Otherwise a terminated CP read could hang the GPU by returning invalid command-stream data. Signed-off-by: Rob Clark ---

[PATCH 12/20] drm/msm: Drop context arg to gpu->submit()

2020-08-24 Thread Rob Clark
From: Jordan Crouse Now that we can get the ctx from the submitqueue, the extra arg is redundant. Signed-off-by: Jordan Crouse [split out of previous patch to reduce churny noise] Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 +---

[PATCH 18/20] arm: dts: qcom: sc7180: Set the compatible string for the GPU SMMU

2020-08-24 Thread Rob Clark
From: Rob Clark Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable split pagetables and per-instance pagetables for drm/msm. Signed-off-by: Rob Clark --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH 17/20] arm: dts: qcom: sm845: Set the compatible string for the GPU SMMU

2020-08-24 Thread Rob Clark
From: Jordan Crouse Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable split pagetables and per-instance pagetables for drm/msm. Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark --- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 9 +

[PATCH 15/20] drm/msm: Add support for private address space instances

2020-08-24 Thread Rob Clark
From: Jordan Crouse Add support for allocating private address space instances. Targets that support per-context pagetables should implement their own function to allocate private address spaces. The default will return a pointer to the global address space. Signed-off-by: Jordan Crouse

[PATCH 20/20] drm/msm: show process names in gem_describe

2020-08-24 Thread Rob Clark
From: Rob Clark In $debugfs/gem we already show any vma(s) associated with an object. Also show process names if the vma's address space is a per-process address space. Signed-off-by: Rob Clark Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_drv.c | 2 +-

[PATCH 10/20] dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU

2020-08-24 Thread Rob Clark
From: Jordan Crouse Every Qcom Adreno GPU has an embedded SMMU for its own use. These devices depend on unique features such as split pagetables, different stall/halt requirements and other settings. Identify them with a compatible string so that they can be identified in the arm-smmu

[PATCH 03/20] iommu/arm-smmu: Add support for split pagetables

2020-08-24 Thread Rob Clark
From: Jordan Crouse Enable TTBR1 for a context bank if IO_PGTABLE_QUIRK_ARM_TTBR1 is selected by the io-pgtable configuration. Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 21 - drivers/iommu/arm/arm-smmu/arm-smmu.h |

[PATCH 01/20] drm/msm: remove dangling submitqueue references

2020-08-24 Thread Rob Clark
From: Rob Clark Currently it doesn't matter, since we free the ctx immediately. But when we start refcnt'ing the ctx, we don't want old dangling list entries to hang around. Signed-off-by: Rob Clark Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_submitqueue.c | 4 +++- 1 file

[PATCH 08/20] iommu/arm-smmu: constify some helpers

2020-08-24 Thread Rob Clark
From: Rob Clark Sprinkle a few `const`s where helpers don't need write access. Signed-off-by: Rob Clark --- drivers/iommu/arm/arm-smmu/arm-smmu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h

[PATCH 06/20] drm/msm/gpu: add dev_to_gpu() helper

2020-08-24 Thread Rob Clark
From: Rob Clark In a later patch, the drvdata will not directly be 'struct msm_gpu *', so add a helper to reduce the churn. Signed-off-by: Rob Clark Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/adreno_device.c | 10 -- drivers/gpu/drm/msm/msm_gpu.c | 6

[PATCH 16/20] drm/msm/a6xx: Add support for per-instance pagetables

2020-08-24 Thread Rob Clark
From: Jordan Crouse Add support for using per-instance pagetables if all the dependencies are available. Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark Reviewed-by: Akhil P Oommen Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 63 +++

Re: [PATCH v2 2/9] iommu/ioasid: Rename ioasid_set_data()

2020-08-24 Thread Jean-Philippe Brucker
On Fri, Aug 21, 2020 at 09:35:11PM -0700, Jacob Pan wrote: > Rename ioasid_set_data() to ioasid_attach_data() to avoid confusion with > struct ioasid_set. ioasid_set is a group of IOASIDs that share a common > token. > > Signed-off-by: Jacob Pan Reviewed-by: Jean-Philippe Brucker > --- >

Re: [PATCH v2 3/9] iommu/ioasid: Introduce ioasid_set APIs

2020-08-24 Thread Jean-Philippe Brucker
On Fri, Aug 21, 2020 at 09:35:12PM -0700, Jacob Pan wrote: > ioasid_set was introduced as an arbitrary token that are shared by a > group of IOASIDs. For example, if IOASID #1 and #2 are allocated via the > same ioasid_set*, they are viewed as to belong to the same set. > > For guest SVA usages,

Re: [PATCH v2 3/9] iommu/ioasid: Introduce ioasid_set APIs

2020-08-24 Thread Randy Dunlap
On 8/24/20 11:28 AM, Jean-Philippe Brucker wrote: >> +/** >> + * struct ioasid_data - Meta data about ioasid >> + * >> + * @id: Unique ID >> + * @users Number of active users >> + * @state Track state of the IOASID >> + * @set Meta data of the set this IOASID belongs to

Re: [PATCH v2 3/9] iommu/ioasid: Introduce ioasid_set APIs

2020-08-24 Thread Randy Dunlap
On 8/24/20 11:28 AM, Jean-Philippe Brucker wrote: >> +/** >> + * struct ioasid_set - Meta data about ioasid_set >> + * @type: Token types and other features > nit: doesn't follow struct order > >> + * @token: Unique to identify an IOASID set >> + * @xa: XArray to store ioasid_set

Re: [RFC v2 4/5] dt-bindings: of: Add plumbing for restricted DMA pool

2020-08-24 Thread Tomasz Figa
On Tue, Aug 11, 2020 at 11:15 AM Tomasz Figa wrote: > > On Mon, Aug 3, 2020 at 5:15 PM Tomasz Figa wrote: > > > > Hi Claire and Rob, > > > > On Mon, Aug 3, 2020 at 4:26 PM Claire Chang wrote: > > > > > > On Sat, Aug 1, 2020 at 4:58 AM Rob Herring wrote: > > > > > > > > On Tue, Jul 28, 2020 at

Is: virtio_gpu_object_shmem_init issues? Was:Re: upstream boot error: general protection fault in swiotlb_map

2020-08-24 Thread Konrad Rzeszutek Wilk
On Thu, Aug 06, 2020 at 03:46:23AM -0700, syzbot wrote: > Hello, > > syzbot found the following issue on: > > HEAD commit:47ec5303 Merge git://git.kernel.org/pub/scm/linux/kernel/g.. > git tree: upstream > console output: https://syzkaller.appspot.com/x/log.txt?x=16fe1dea90 >

Re: Is: virtio_gpu_object_shmem_init issues? Was:Re: upstream boot error: general protection fault in swiotlb_map

2020-08-24 Thread Dmitry Vyukov via iommu
On Mon, Aug 24, 2020 at 5:07 PM Konrad Rzeszutek Wilk wrote: > > On Thu, Aug 06, 2020 at 03:46:23AM -0700, syzbot wrote: > > Hello, > > > > syzbot found the following issue on: > > > > HEAD commit:47ec5303 Merge git://git.kernel.org/pub/scm/linux/kernel/g.. > > git tree: upstream > >

[PATCH AUTOSEL 5.8 31/63] dma-pool: Only allocate from CMA when in same memory zone

2020-08-24 Thread Sasha Levin
From: Nicolas Saenz Julienne [ Upstream commit d7e673ec2c8e0ea39c4c70fc490d67d7fbda869d ] There is no guarantee to CMA's placement, so allocating a zone specific atomic pool from CMA might return memory from a completely different memory zone. To get around this double check CMA's placement

[PATCH AUTOSEL 5.8 30/63] dma-pool: fix coherent pool allocations for IOMMU mappings

2020-08-24 Thread Sasha Levin
From: Christoph Hellwig [ Upstream commit 9420139f516d7fbc248ce17f35275cb005ed98ea ] When allocating coherent pool memory for an IOMMU mapping we don't care about the DMA mask. Move the guess for the initial GFP mask into the dma_direct_alloc_pages and pass dma_coherent_ok as a function

Re: [PATCH 17/18] media/omap3isp: Clean up IOMMU workaround

2020-08-24 Thread Suman Anna via iommu
On 8/20/20 6:01 PM, Robin Murphy wrote: > On 2020-08-20 20:55, Sakari Ailus wrote: >> On Thu, Aug 20, 2020 at 06:25:19PM +0100, Robin Murphy wrote: >>> On 2020-08-20 17:53, Sakari Ailus wrote: Hi Robin, On Thu, Aug 20, 2020 at 04:08:36PM +0100, Robin Murphy wrote: > Now that

Re: [PATCH] dt-bindings: iommu: renesas,ipmmu-vmsa: Sort compatible string in increasing number of the SoC

2020-08-24 Thread Rob Herring
On Sun, 09 Aug 2020 20:35:27 +0100, Lad Prabhakar wrote: > Sort the items in the compatible string list in increasing number of SoC. > > Signed-off-by: Lad Prabhakar > --- > Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >

Re: [PATCH] iommu/intel: Handle 36b addressing for x86-32

2020-08-24 Thread Lu Baolu
Hi Chris, On 2020/8/23 0:02, Chris Wilson wrote: Beware that the address size for x86-32 may exceed unsigned long. [0.368971] UBSAN: shift-out-of-bounds in drivers/iommu/intel/iommu.c:128:14 [0.369055] shift exponent 36 is too large for 32-bit type 'long unsigned int' If we don't

Re: [PATCH v4 07/15] iommu/vt-d: Delegate the dma domain to upper layer

2020-08-24 Thread Lu Baolu
Hi Chris, On 8/24/20 4:35 PM, Chris Wilson wrote: Quoting Lu Baolu (2020-08-24 07:31:23) Hi Chris, On 2020/8/22 2:33, Chris Wilson wrote: Quoting Lu Baolu (2019-05-25 06:41:28) This allows the iommu generic layer to allocate a dma domain and attach it to a device through the iommu api's.

Re: [patch RFC 24/38] x86/xen: Consolidate XEN-MSI init

2020-08-24 Thread Jürgen Groß
On 24.08.20 23:21, Thomas Gleixner wrote: On Mon, Aug 24 2020 at 06:59, Jürgen Groß wrote: On 21.08.20 02:24, Thomas Gleixner wrote: +static __init void xen_setup_pci_msi(void) +{ + if (xen_initial_domain()) { + x86_msi.setup_msi_irqs = xen_initdom_setup_msi_irqs; +

[PATCH v11 07/11] device-mapping: Introduce DMA range map, supplanting dma_pfn_offset

2020-08-24 Thread Jim Quinlan via iommu
The new field 'dma_range_map' in struct device is used to facilitate the use of single or multiple offsets between mapping regions of cpu addrs and dma addrs. It subsumes the role of "dev->dma_pfn_offset" which was only capable of holding a single uniform offset and had no region bounds checking.

[PATCH v11 00/11] PCI: brcmstb: enable PCIe for STB chips

2020-08-24 Thread Jim Quinlan via iommu
Patchset Summary: Enhance a PCIe host controller driver. Because of its unusual design we are foced to change dev->dma_pfn_offset into a more general role allowing multiple offsets. See the 'v1' notes below for more info. v11: Commit: "device-mapping: Introduce DMA range map,

Re: [patch RFC 24/38] x86/xen: Consolidate XEN-MSI init

2020-08-24 Thread Thomas Gleixner
On Mon, Aug 24 2020 at 06:59, Jürgen Groß wrote: > On 21.08.20 02:24, Thomas Gleixner wrote: >> +static __init void xen_setup_pci_msi(void) >> +{ >> +if (xen_initial_domain()) { >> +x86_msi.setup_msi_irqs = xen_initdom_setup_msi_irqs; >> +x86_msi.teardown_msi_irqs =

Re: [PATCH 11/18] iommu/omap: Add IOMMU_DOMAIN_DMA support

2020-08-24 Thread Suman Anna via iommu
Hi Robin, On 8/20/20 10:08 AM, Robin Murphy wrote: > Now that arch/arm is wired up for default domains and iommu-dma, > implement the corresponding driver-side support for DMA domains. > > Signed-off-by: Robin Murphy > --- > drivers/iommu/omap-iommu.c | 22 +- > 1 file