Re: a saner API for allocating DMA addressable pages v2

2020-09-15 Thread Christoph Hellwig
On Mon, Sep 14, 2020 at 04:26:17PM +0100, Matthew Wilcox wrote: > On Mon, Sep 14, 2020 at 04:44:16PM +0200, Christoph Hellwig wrote: > > I'm still a little unsure about the API naming, as alloc_pages sort of > > implies a struct page return value, but we return a kernel virtual > > address. > >

Re: [PATCH] irqchip/qcom-pdc: Allow QCOM_PDC to be loadable as a permanent module

2020-09-15 Thread Greg Kroah-Hartman
On Mon, Sep 14, 2020 at 09:04:23PM +, John Stultz wrote: > Allows qcom-pdc driver to be loaded as a permanent module. > > An earlier version of this patch was merged in a larger patchset > but was reverted entirely when issues were found with other > drivers, so now that Marc has provided a

Re: [PATCH 11/17] sgiseeq: convert to dma_alloc_noncoherent

2020-09-15 Thread Christoph Hellwig
On Mon, Sep 14, 2020 at 04:13:58PM +0100, Matthew Wilcox wrote: > On Mon, Sep 14, 2020 at 04:44:27PM +0200, Christoph Hellwig wrote: > > drivers/net/ethernet/i825xx/lasi_82596.c | 25 ++--- > > drivers/net/ethernet/i825xx/lib82596.c | 114 ++- > >

Re: [PATCHv4 6/6] iommu: arm-smmu-impl: Remove unwanted extra blank lines

2020-09-15 Thread Sai Prakash Ranjan
On 2020-09-11 22:20, Sai Prakash Ranjan wrote: On 2020-09-11 22:04, Robin Murphy wrote: On 2020-09-11 17:21, Sai Prakash Ranjan wrote: On 2020-09-11 21:37, Will Deacon wrote: On Fri, Sep 11, 2020 at 05:03:06PM +0100, Robin Murphy wrote: BTW am I supposed to have received 3 copies of

Re: [PATCH 03/17] drm/exynos: stop setting DMA_ATTR_NON_CONSISTENT

2020-09-15 Thread Christoph Hellwig
On Mon, Sep 14, 2020 at 06:34:02PM +0300, Sergei Shtylyov wrote: > On 9/14/20 5:44 PM, Christoph Hellwig wrote: > > > DMA_ATTR_NON_CONSISTENT is a no-op except on PARISC and some mips > > configs, so don't set it in this ARM specific driver. > >Hm, PARICS and ARM capitalized but mips in

Re: [PATCH v3 0/6] Convert the intel iommu driver to the dma-iommu api

2020-09-15 Thread Tvrtko Ursulin
On 15/09/2020 02:47, Lu Baolu wrote: Hi Tvrtko, On 9/14/20 4:04 PM, Tvrtko Ursulin wrote: Hi, On 12/09/2020 04:21, Lu Baolu wrote: Tom Murphy has almost done all the work. His latest patch series was posted here. https://lore.kernel.org/linux-iommu/20200903201839.7327-1-murph...@tcd.ie/

Re: [trivial PATCH] treewide: Convert switch/case fallthrough; to break;

2020-09-15 Thread Miquel Raynal
Hi Joe, For MTD: > drivers/mtd/nand/raw/nandsim.c| 2 +- Reviewed-by: Miquel Raynal Thanks, Miquèl ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu

Re: [PATCH 07/17] 53c700: improve non-coherent DMA handling

2020-09-15 Thread Christoph Hellwig
On Mon, Sep 14, 2020 at 08:20:18AM -0700, James Bottomley wrote: > If you're going to change the macros from taking a device to taking a > hostdata structure then the descriptive argument name needs to change > ... it can't be dev anymore. I'm happy with it simply becoming 'h' if > hostdata is

Re: [Intel-gfx] [trivial PATCH] treewide: Convert switch/case fallthrough; to break;

2020-09-15 Thread Jani Nikula
On Wed, 09 Sep 2020, Joe Perches wrote: > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c > b/drivers/gpu/drm/i915/display/intel_sprite.c > index 5ac0dbf0e03d..35ac539cc2b1 100644 > --- a/drivers/gpu/drm/i915/display/intel_sprite.c > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c >

Re: [PATCH] iommu/amd: fix interrupt remapping for avic

2020-09-15 Thread Maxim Levitsky
On Mon, 2020-09-14 at 21:48 +0700, Suravee Suthikulpanit wrote: > Maxim, > > On 9/13/2020 7:42 PM, Maxim Levitsky wrote: > > Commit e52d58d54a32 ("iommu/amd: Use cmpxchg_double() when updating 128-bit > > IRTE") > > accidentally removed an assumption that modify_irte_ga always set the valid > >

[PATCH] dma-direct: Fix potential NULL pointer dereference

2020-09-15 Thread Thomas Tai
When booting the kernel v5.9-rc4 on a VM, the kernel would panic when printing a warning message in swiotlb_map(). It is because dev->dma_mask can potentially be a null pointer. Using the dma_get_mask() macro can avoid the NULL pointer dereference. Fixes: d323bb44e4d2 ("drm/virtio: Call the right

Re: [PATCH] iommu/amd: fix interrupt remapping for avic

2020-09-15 Thread Suravee Suthikulpanit
On 9/15/20 6:25 PM, Maxim Levitsky wrote: On Mon, 2020-09-14 at 21:48 +0700, Suravee Suthikulpanit wrote: Maxim, On 9/13/2020 7:42 PM, Maxim Levitsky wrote: Commit e52d58d54a32 ("iommu/amd: Use cmpxchg_double() when updating 128-bit IRTE") accidentally removed an assumption that

Re: [PATCH] iommu/amd: fix interrupt remapping for avic

2020-09-15 Thread Joao Martins
On 9/15/20 1:30 PM, Suravee Suthikulpanit wrote: > On 9/15/20 6:25 PM, Maxim Levitsky wrote: >> On Mon, 2020-09-14 at 21:48 +0700, Suravee Suthikulpanit wrote: >>> Could you please try with the following patch instead? >>> >>> --- a/drivers/iommu/amd/iommu.c >>> +++ b/drivers/iommu/amd/iommu.c >>>

Re: [PATCH] dma-direct: Fix potential NULL pointer dereference

2020-09-15 Thread Thomas Tai
On 2020-09-15 10:07 a.m., Christoph Hellwig wrote: On Tue, Sep 15, 2020 at 08:03:14AM -0600, Thomas Tai wrote: When booting the kernel v5.9-rc4 on a VM, the kernel would panic when printing a warning message in swiotlb_map(). It is because dev->dma_mask can potentially be a null pointer.

Re: [PATCH 07/17] 53c700: improve non-coherent DMA handling

2020-09-15 Thread James Bottomley
On Tue, 2020-09-15 at 08:27 +0200, Christoph Hellwig wrote: > On Mon, Sep 14, 2020 at 08:20:18AM -0700, James Bottomley wrote: > > If you're going to change the macros from taking a device to taking > > a hostdata structure then the descriptive argument name needs to > > change ... it can't be dev

Re: [PATCH v7 00/16] vfio: expose virtual Shared Virtual Addressing to VMs

2020-09-15 Thread Jason Gunthorpe
On Mon, Sep 14, 2020 at 03:44:38PM -0700, Raj, Ashok wrote: > Hi Jason, > > I thought we discussed this at LPC, but still seems to be going in > circles :-(. We discused mdev at LPC, not PASID. PASID applies widely to many device and needs to be introduced with a wide community agreement so all

Re: [PATCH] dma-direct: Fix potential NULL pointer dereference

2020-09-15 Thread Christoph Hellwig
On Tue, Sep 15, 2020 at 04:07:19PM +0200, Christoph Hellwig wrote: > On Tue, Sep 15, 2020 at 08:03:14AM -0600, Thomas Tai wrote: > > When booting the kernel v5.9-rc4 on a VM, the kernel would panic when > > printing a warning message in swiotlb_map(). It is because dev->dma_mask > > can

Re: [PATCH v2 1/4] dt-bindings: reserved-memory: Document "active" property

2020-09-15 Thread Thierry Reding
On Mon, Sep 14, 2020 at 04:08:29PM -0600, Rob Herring wrote: > On Fri, Sep 04, 2020 at 02:59:57PM +0200, Thierry Reding wrote: > > From: Thierry Reding > > > > Reserved memory regions can be marked as "active" if hardware is > > expected to access the regions during boot and before the operating

Re: [PATCH] dma-direct: Fix potential NULL pointer dereference

2020-09-15 Thread Christoph Hellwig
On Tue, Sep 15, 2020 at 08:03:14AM -0600, Thomas Tai wrote: > When booting the kernel v5.9-rc4 on a VM, the kernel would panic when > printing a warning message in swiotlb_map(). It is because dev->dma_mask > can potentially be a null pointer. Using the dma_get_mask() macro can > avoid the NULL

Re: [PATCH v7 00/16] vfio: expose virtual Shared Virtual Addressing to VMs

2020-09-15 Thread Jason Gunthorpe
On Mon, Sep 14, 2020 at 04:33:10PM -0600, Alex Williamson wrote: > Can you explain that further, or spit-ball what you think this /dev/sva > interface looks like and how a user might interact between vfio and > this new interface? When you open it you get some container, inside the container

Re: [PATCH] dma-direct: Fix potential NULL pointer dereference

2020-09-15 Thread Christoph Hellwig
On Tue, Sep 15, 2020 at 10:11:51AM -0400, Thomas Tai wrote: > > > On 2020-09-15 10:07 a.m., Christoph Hellwig wrote: >> On Tue, Sep 15, 2020 at 08:03:14AM -0600, Thomas Tai wrote: >>> When booting the kernel v5.9-rc4 on a VM, the kernel would panic when >>> printing a warning message in

[PATCH 02/18] mm: turn alloc_pages into an inline function

2020-09-15 Thread Christoph Hellwig
To prevent a compiler error when a method call alloc_pages is added (which I plan to for the dma_map_ops). Signed-off-by: Christoph Hellwig --- include/linux/gfp.h | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/include/linux/gfp.h b/include/linux/gfp.h index

[PATCH 08/18] dma-mapping: add a new dma_alloc_noncoherent API

2020-09-15 Thread Christoph Hellwig
Add a new API to allocate and free memory that is guaranteed to be addressable by a device, but which potentially is not cache coherent for DMA. To transfer ownership to and from the device, the existing streaming DMA API calls dma_sync_single_for_device and dma_sync_single_for_cpu must be used.

[PATCH 13/18] 53c700: convert to dma_alloc_noncoherent

2020-09-15 Thread Christoph Hellwig
Use the new non-coherent DMA API including proper ownership transfers. Signed-off-by: Christoph Hellwig --- drivers/scsi/53c700.c | 20 ++-- 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/scsi/53c700.c b/drivers/scsi/53c700.c index

[PATCH v8 9/9] x86/mmu: Allocate/free PASID

2020-09-15 Thread Fenghua Yu
A PASID is allocated for an "mm" the first time any thread binds to an SVM capable device and is freed from the "mm" when the SVM is unbound by the last thread. It's possible for the "mm" to have different PASID values in different binding/unbinding SVM cycles. The mm's PASID (non-zero for valid

[PATCH v8 7/9] mm: Define pasid in mm

2020-09-15 Thread Fenghua Yu
PASID is shared by all threads in a process. So the logical place to keep track of it is in the "mm". Both ARM and X86 need to use the PASID in the "mm". Suggested-by: Christoph Hellwig Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v4: - Change PASID type to u32 (Christoph) v3: -

[PATCH v8 1/9] drm, iommu: Change type of pasid to u32

2020-09-15 Thread Fenghua Yu
PASID is defined as a few different types in iommu including "int", "u32", and "unsigned int". To be consistent and to match with uapi definitions, define PASID and its variations (e.g. max PASID) as "u32". "u32" is also shorter and a little more explicit than "unsigned int". No PASID type change

[PATCH v8 5/9] x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature

2020-09-15 Thread Fenghua Yu
From: Yu-cheng Yu ENQCMD instruction reads PASID from IA32_PASID MSR. The MSR is stored in the task's supervisor FPU PASID state and is context switched by XSAVES/XRSTORS. Signed-off-by: Yu-cheng Yu Co-developed-by: Fenghua Yu Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: -

[PATCH v8 0/9] x86: tag application address space for devices

2020-09-15 Thread Fenghua Yu
Typical hardware devices require a driver stack to translate application buffers to hardware addresses, and a kernel-user transition to notify the hardware of new work. What if both the translation and transition overhead could be eliminated? This is what Shared Virtual Address (SVA) and ENQCMD

[PATCH v8 4/9] x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions

2020-09-15 Thread Fenghua Yu
Work submission instruction comes in two flavors. ENQCMD can be called both in ring 3 and ring 0 and always uses the contents of PASID MSR when shipping the command to the device. ENQCMDS allows a kernel driver to submit commands on behalf of a user process. The driver supplies the PASID value in

[PATCH v8 8/9] x86/cpufeatures: Mark ENQCMD as disabled when configured out

2020-09-15 Thread Fenghua Yu
Currently, the ENQCMD feature depends on CONFIG_IOMMU_SUPPORT. Add X86_FEATURE_ENQCMD to the disabled features mask. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v8: - Re-write commit message (Boris). - Move "#ifdef CONFIG_IOMMU_SUPPORT" hunk from patch 9 (Boris). v7: - Split this

[PATCH 01/18] media/v4l2: remove V4L2-FLAG-MEMORY-NON-CONSISTENT flag

2020-09-15 Thread Christoph Hellwig
From: Sergey Senozhatsky The patch partially reverts some of the UAPI bits of the buffer cache management hints. Namely, the queue consistency (memory coherency) user-space hint because, as it turned out, the kernel implementation of this feature was misusing DMA_ATTR_NON_CONSISTENT. The patch

[PATCH 18/18] firewire-ohci: use dma_alloc_pages

2020-09-15 Thread Christoph Hellwig
Use dma_alloc_pages to allocate DMAable pages instead of hoping that the architecture either has GFP_DMA32 or not more than 4G of memory. Signed-off-by: Christoph Hellwig --- drivers/firewire/ohci.c | 26 +++--- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git

Re: [PATCH] dma-direct: Fix potential NULL pointer dereference

2020-09-15 Thread Christoph Hellwig
On Tue, Sep 15, 2020 at 10:40:39AM -0400, Thomas Tai wrote: >> +++ b/include/linux/dma-direct.h >> @@ -62,9 +62,6 @@ static inline bool dma_capable(struct device *dev, >> dma_addr_t addr, size_t size, >> { >> dma_addr_t end = addr + size - 1; >> - if (!dev->dma_mask) >> -

Re: [PATCH] irqchip/qcom-pdc: Allow QCOM_PDC to be loadable as a permanent module

2020-09-15 Thread Bjorn Andersson
On Mon 14 Sep 21:04 UTC 2020, John Stultz wrote: > Allows qcom-pdc driver to be loaded as a permanent module. > > An earlier version of this patch was merged in a larger patchset > but was reverted entirely when issues were found with other > drivers, so now that Marc has provided a better

a saner API for allocating DMA addressable pages v3

2020-09-15 Thread Christoph Hellwig
Hi all, this series replaced the DMA_ATTR_NON_CONSISTENT flag to dma_alloc_attrs with a separate new dma_alloc_pages API, which is available on all platforms. In addition to cleaning up the convoluted code path, this ensures that other drivers that have asked for better support for non-coherent

[PATCH 03/18] drm/exynos: stop setting DMA_ATTR_NON_CONSISTENT

2020-09-15 Thread Christoph Hellwig
DMA_ATTR_NON_CONSISTENT is a no-op except on PA-RISC and a few MIPS configs, so don't set it in this ARM specific driver. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/exynos/exynos_drm_gem.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c

[PATCH 06/18] lib82596: move DMA allocation into the callers of i82596_probe

2020-09-15 Thread Christoph Hellwig
This allows us to get rid of the LIB82596_DMA_ATTR defined and prepare for untangling the coherent vs non-coherent DMA allocation API. Signed-off-by: Christoph Hellwig --- drivers/net/ethernet/i825xx/lasi_82596.c | 24 ++-- drivers/net/ethernet/i825xx/lib82596.c | 36

[PATCH 09/18] sgiwd93: convert to dma_alloc_noncoherent

2020-09-15 Thread Christoph Hellwig
Use the new non-coherent DMA API including proper ownership transfers. This also means we can allocate the memory as DMA_TO_DEVICE instead of bidirectional. Signed-off-by: Christoph Hellwig --- drivers/scsi/sgiwd93.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff

[PATCH 14/18] dma-mapping: remove dma_cache_sync

2020-09-15 Thread Christoph Hellwig
All users are gone now, remove the API. Signed-off-by: Christoph Hellwig --- arch/mips/Kconfig | 1 - arch/mips/jazz/jazzdma.c| 1 - arch/mips/mm/dma-noncoherent.c | 6 -- arch/parisc/Kconfig | 1 - arch/parisc/kernel/pci-dma.c| 6 --

[PATCH v8 6/9] x86/msr-index: Define IA32_PASID MSR

2020-09-15 Thread Fenghua Yu
The IA32_PASID MSR (0xd93) contains the Process Address Space Identifier (PASID), a 20-bit value. Bit 31 must be set to indicate the value programmed in the MSR is valid. Hardware uses PASID to identify process address space and direct responses to the right address space. Signed-off-by: Fenghua

[PATCH v8 2/9] iommu/vt-d: Change flags type to unsigned int in binding mm

2020-09-15 Thread Fenghua Yu
"flags" passed to intel_svm_bind_mm() is a bit mask and should be defined as "unsigned int" instead of "int". Change its type to "unsigned int". Suggested-by: Thomas Gleixner Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck Reviewed-by: Lu Baolu --- v5: - Reviewed by Lu Baolu v2: - Add this

[PATCH v8 3/9] Documentation/x86: Add documentation for SVA (Shared Virtual Addressing)

2020-09-15 Thread Fenghua Yu
From: Ashok Raj ENQCMD and Data Streaming Accelerator (DSA) and all of their associated features are a complicated stack with lots of interconnected pieces. This documentation provides a big picture overview for all of the features. Signed-off-by: Ashok Raj Co-developed-by: Fenghua Yu

[PATCH 17/18] dma-iommu: implement ->alloc_noncoherent

2020-09-15 Thread Christoph Hellwig
Implement the alloc_noncoherent method to provide memory that is neither coherent not contiguous. Signed-off-by: Christoph Hellwig --- drivers/iommu/dma-iommu.c | 41 +++ 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/dma-iommu.c

Re: [PATCH] dma-direct: Fix potential NULL pointer dereference

2020-09-15 Thread Thomas Tai
On 2020-09-15 11:09 a.m., Christoph Hellwig wrote: On Tue, Sep 15, 2020 at 10:40:39AM -0400, Thomas Tai wrote: +++ b/include/linux/dma-direct.h @@ -62,9 +62,6 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size, { dma_addr_t end = addr + size - 1;

[PATCH 04/18] drm/nouveau/gk20a: stop setting DMA_ATTR_NON_CONSISTENT

2020-09-15 Thread Christoph Hellwig
DMA_ATTR_NON_CONSISTENT is a no-op except on PA-RISC and a few MIPS configs, so don't set it in this ARM specific driver part. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git

[PATCH 11/18] lib82596: convert to dma_alloc_noncoherent

2020-09-15 Thread Christoph Hellwig
Use the new non-coherent DMA API including proper ownership transfers. This includes moving the DMA helpers to lib82596 based of an ifdef to avoid include order problems. Signed-off-by: Christoph Hellwig --- drivers/net/ethernet/i825xx/lasi_82596.c | 25 ++---

[PATCH 05/18] net/au1000-eth: stop using DMA_ATTR_NON_CONSISTENT

2020-09-15 Thread Christoph Hellwig
The au1000-eth driver contains none of the manual cache synchronization required for using DMA_ATTR_NON_CONSISTENT. From what I can tell it can be used on both dma coherent and non-coherent DMA platforms, but I suspect it has been buggy on the non-coherent platforms all along. Signed-off-by:

[PATCH 15/18] dma-mapping: add a new dma_alloc_pages API

2020-09-15 Thread Christoph Hellwig
This API is the equivalent of alloc_pages, except that the returned memory is guaranteed to be DMA addressable by the passed in device. The implementation will also be used to provide a more sensible replacement for DMA_ATTR_NON_CONSISTENT flag. Additionally dma_alloc_noncoherent is switched

Re: [PATCH] dma-direct: Fix potential NULL pointer dereference

2020-09-15 Thread Thomas Tai
On 2020-09-15 10:26 a.m., Christoph Hellwig wrote: On Tue, Sep 15, 2020 at 10:11:51AM -0400, Thomas Tai wrote: On 2020-09-15 10:07 a.m., Christoph Hellwig wrote: On Tue, Sep 15, 2020 at 08:03:14AM -0600, Thomas Tai wrote: When booting the kernel v5.9-rc4 on a VM, the kernel would panic

[PATCH 07/18] 53c700: improve non-coherent DMA handling

2020-09-15 Thread Christoph Hellwig
Switch the 53c700 driver to only use non-coherent descriptor memory if it really has to because dma_alloc_coherent fails. This doesn't matter for any of the platforms it runs on currently, but that will change soon. To help with this two new helpers to transfer ownership to and from the device

[PATCH 12/18] sgiseeq: convert to dma_alloc_noncoherent

2020-09-15 Thread Christoph Hellwig
Use the new non-coherent DMA API including proper ownership transfers. This includes adding additional calls to dma_sync_desc_dev as the old syncing was rather ad-hoc. Thanks to Thomas Bogendoerfer for debugging the ownership transfer issues. Signed-off-by: Christoph Hellwig ---

[PATCH 16/18] dma-mapping: add new {alloc, free}_noncoherent dma_map_ops methods

2020-09-15 Thread Christoph Hellwig
This will allow IOMMU drivers to allocate non-contigous memory and return a vmapped virtual address. Signed-off-by: Christoph Hellwig --- include/linux/dma-mapping.h | 5 + kernel/dma/mapping.c| 33 +++-- 2 files changed, 32 insertions(+), 6 deletions(-)

[PATCH 10/18] hal2: convert to dma_alloc_noncoherent

2020-09-15 Thread Christoph Hellwig
Use the new non-coherent DMA API including proper ownership transfers. This also means we can allocate the buffer memory with the proper direction instead of bidirectional. Signed-off-by: Christoph Hellwig --- sound/mips/hal2.c | 58 ++- 1 file

Re: [PATCH v7 00/16] vfio: expose virtual Shared Virtual Addressing to VMs

2020-09-15 Thread Raj, Ashok
On Tue, Sep 15, 2020 at 08:33:41AM -0300, Jason Gunthorpe wrote: > On Mon, Sep 14, 2020 at 03:44:38PM -0700, Raj, Ashok wrote: > > Hi Jason, > > > > I thought we discussed this at LPC, but still seems to be going in > > circles :-(. > > We discused mdev at LPC, not PASID. > > PASID applies

Re: [PATCH v7 00/16] vfio: expose virtual Shared Virtual Addressing to VMs

2020-09-15 Thread Raj, Ashok
On Tue, Sep 15, 2020 at 03:45:10PM -0300, Jason Gunthorpe wrote: > On Tue, Sep 15, 2020 at 11:11:54AM -0700, Raj, Ashok wrote: > > > PASID applies widely to many device and needs to be introduced with a > > > wide community agreement so all scenarios will be supportable. > > > > True, reading

Re: [PATCH 6/6] dma-mapping: introduce DMA range map, supplanting dma_pfn_offset

2020-09-15 Thread Mathieu Poirier
On Tue, Sep 15, 2020 at 07:41:22AM +0200, Christoph Hellwig wrote: > On Mon, Sep 14, 2020 at 05:01:47PM -0600, Mathieu Poirier wrote: > > [700 lines of the fullquote deleted..] > > > > + for (r = map; r->size; r++) > > > + num_ranges++; > > > + > > > + new_map = kmemdup(map,

[PATCH v2] iommu: Kconfig: Update help description for IPMMU_VMSA config

2020-09-15 Thread Lad Prabhakar
ipmmu-vmsa driver is also used on Renesas RZ/G{1,2} Soc's, update the description for the IPMMU_VMSA config symbol to reflect this. Signed-off-by: Lad Prabhakar Reviewed-by: Chris Paterson Reviewed-by: Geert Uytterhoeven --- v1->v2 * Updated commit description as suggested by Geert * Included

Re: [PATCH v7 00/16] vfio: expose virtual Shared Virtual Addressing to VMs

2020-09-15 Thread Jason Gunthorpe
On Tue, Sep 15, 2020 at 11:11:54AM -0700, Raj, Ashok wrote: > > PASID applies widely to many device and needs to be introduced with a > > wide community agreement so all scenarios will be supportable. > > True, reading some of the earlier replies I was clearly confused as I > thought you were

Re: [PATCH] dma-direct: Fix potential NULL pointer dereference

2020-09-15 Thread Thomas Tai
On 2020-09-15 11:09 a.m., Christoph Hellwig wrote: On Tue, Sep 15, 2020 at 10:40:39AM -0400, Thomas Tai wrote: +++ b/include/linux/dma-direct.h @@ -62,9 +62,6 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size, { dma_addr_t end = addr + size - 1;

[PATCH] iommu/tegra-smmu: Fix tlb_mask

2020-09-15 Thread Nicolin Chen
The "num_tlb_lines" might not be a power-of-2 value, being 48 on Tegra210 for example. So the current way of calculating tlb_mask using the num_tlb_lines is not correct: tlb_mask=0x5f in case of num_tlb_lines=48, which will trim a setting of 0x30 (48) to 0x10. Signed-off-by: Nicolin Chen ---

Re: [PATCH v7 00/16] vfio: expose virtual Shared Virtual Addressing to VMs

2020-09-15 Thread Lu Baolu
On 9/16/20 8:22 AM, Jacob Pan (Jun) wrote: If user space wants to bind page tables, create the PASID with /dev/sva, use ioctls there to setup the page table the way it wants, then pass the now configured PASID to a driver that can use it. Are we talking about bare metal SVA? If so, I don't see

Re: [PATCH v7 00/16] vfio: expose virtual Shared Virtual Addressing to VMs

2020-09-15 Thread Jason Wang
On 2020/9/14 下午9:31, Jean-Philippe Brucker wrote: If it's possible, I would suggest a generic uAPI instead of a VFIO specific one. A large part of this work is already generic uAPI, in include/uapi/linux/iommu.h. This is not what I read from this series, all the following uAPI is VFIO

Re: [PATCH v7 00/16] vfio: expose virtual Shared Virtual Addressing to VMs

2020-09-15 Thread Jason Gunthorpe
On Tue, Sep 15, 2020 at 12:26:32PM -0700, Raj, Ashok wrote: > > Yes, there is. There is a limited pool of HW PASID's. If one user fork > > bombs it can easially claim an unreasonable number from that pool as > > each process will claim a PASID. That can DOS the rest of the system. > > Not sure

Re: [PATCH v7 00/16] vfio: expose virtual Shared Virtual Addressing to VMs

2020-09-15 Thread Jacob Pan
Hi Jason, On Tue, 15 Sep 2020 15:45:10 -0300, Jason Gunthorpe wrote: > On Tue, Sep 15, 2020 at 11:11:54AM -0700, Raj, Ashok wrote: > > > PASID applies widely to many device and needs to be introduced with a > > > wide community agreement so all scenarios will be supportable. > > > > True,

Re: [PATCH v4 4/4] PCI/ACS: Enable PCI_ACS_TB for untrusted/external-facing devices

2020-09-15 Thread Rajat Jain via iommu
Hello Bjorn, On Tue, Jul 14, 2020 at 1:19 PM Rajat Jain wrote: > > On Sat, Jul 11, 2020 at 12:53 PM Bjorn Helgaas wrote: > > > > On Fri, Jul 10, 2020 at 03:53:59PM -0700, Rajat Jain wrote: > > > On Fri, Jul 10, 2020 at 2:29 PM Raj, Ashok wrote: > > > > On Fri, Jul 10, 2020 at 03:29:22PM

Re: [PATCH v7 00/16] vfio: expose virtual Shared Virtual Addressing to VMs

2020-09-15 Thread Jacob Pan (Jun)
Hi Jason, On Tue, 15 Sep 2020 20:51:26 -0300, Jason Gunthorpe wrote: > On Tue, Sep 15, 2020 at 03:08:51PM -0700, Jacob Pan wrote: > > > A PASID vIOMMU solution sharable with VDPA and VFIO, based on a > > > PASID control char dev (eg /dev/sva, or maybe /dev/iommu) seems > > > like a reasonable

RE: [PATCH v7 00/16] vfio: expose virtual Shared Virtual Addressing to VMs

2020-09-15 Thread Tian, Kevin
> From: Jason Gunthorpe > Sent: Tuesday, September 15, 2020 10:29 PM > > > Do they need a device at all? It's not clear to me why RID based > > IOMMU management fits within vfio's scope, but PASID based does not. > > In RID mode vfio-pci completely owns the PCI function, so it is more > natural

[PATCH 2/3] drm/panfrost: Support cache-coherent integrations

2020-09-15 Thread Robin Murphy
When the GPU's ACE-Lite interface is fully wired up and capable of snooping CPU caches, it may be described as "dma-coherent" in devicetree, which will already inform the DMA layer not to perform unnecessary cache maintenance. However, we still need to ensure that the GPU uses the appropriate

[PATCH 3/3] arm64: dts: meson: Describe G12b GPU as coherent

2020-09-15 Thread Robin Murphy
According to a downstream commit I found in the Khadas vendor kernel, the GPU on G12b is wired up for ACE-lite, so (now that Panfrost knows how to handle this properly) we should describe it as such. Otherwise the mismatch leads to all manner of fun with mismatched attributes and inadvertently

Re: [PATCH v7 00/16] vfio: expose virtual Shared Virtual Addressing to VMs

2020-09-15 Thread Jason Gunthorpe
On Tue, Sep 15, 2020 at 03:08:51PM -0700, Jacob Pan wrote: > > A PASID vIOMMU solution sharable with VDPA and VFIO, based on a PASID > > control char dev (eg /dev/sva, or maybe /dev/iommu) seems like a > > reasonable starting point for discussion. > > I am not sure what can really be consolidated

[PATCH 1/3] iommu/io-pgtable-arm: Support coherency for Mali LPAE

2020-09-15 Thread Robin Murphy
Midgard GPUs have ACE-Lite master interfaces which allows systems to integrate them in an I/O-coherent manner. It seems that from the GPU's viewpoint, the rest of the system is its outer shareable domain, and so even when snoop signals are wired up, they are only emitted for outer shareable

[PATCH 0/3] drm: panfrost: Coherency support

2020-09-15 Thread Robin Murphy
Hi all, I polished up my original proof-of-concept a little while back, but now that I've got my hands on my Juno again I've been able to actually test it to my satisfaction, so here are proper patches! It probably makes sense for patches #1 and #2 to stay together and both go via drm-misc,

Re: [PATCH v7 00/16] vfio: expose virtual Shared Virtual Addressing to VMs

2020-09-15 Thread Jason Wang
On 2020/9/16 上午3:26, Raj, Ashok wrote: IIUC, you are asking that part of the interface to move to a API interface that potentially the new /dev/sva and VFIO could share? I think the API's for PASID management themselves are generic (Jean's patchset + Jacob's ioasid set management). Yes, the in