Re: [Intel-gfx] [PATCH v3 0/6] Convert the intel iommu driver to the dma-iommu api

2020-09-22 Thread Logan Gunthorpe
On 2020-09-22 3:51 a.m., Robin Murphy wrote: > On 2020-09-18 21:47, Logan Gunthorpe wrote: >> Hi Lu, >> >> On 2020-09-11 9:21 p.m., Lu Baolu wrote: >>> Tom Murphy has almost done all the work. His latest patch series was >>> posted here. >>> >>>

[PATCHv5 0/6] System Cache support for GPU and required SMMU support

2020-09-22 Thread Sai Prakash Ranjan
Some hardware variants contain a system cache or the last level cache(llc). This cache is typically a large block which is shared by multiple clients on the SOC. GPU uses the system cache to cache both the GPU data buffers(like textures) as well the SMMU pagetables. This helps with improved render

Re: [PATCH v5 05/38] drm: prime: use sgtable iterators in drm_prime_sg_to_page_addr_arrays()

2020-09-22 Thread Marek Szyprowski
Hi Alex, On 22.09.2020 01:15, Alex Goins wrote: > Tested-by: Alex Goins > > This change fixes a regression with drm_prime_sg_to_page_addr_arrays() and > AMDGPU in v5.9. Thanks for testing! > Commit 39913934 similarly revamped AMDGPU to use sgtable helper functions. > When > it changed from

Re: [PATCHv4 1/6] iommu/io-pgtable-arm: Add support to use system cache

2020-09-22 Thread Sai Prakash Ranjan
Hi Will, On 2020-09-21 23:33, Will Deacon wrote: On Fri, Sep 11, 2020 at 07:57:18PM +0530, Sai Prakash Ranjan wrote: Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the attributes set in TCR for the page table walker when using system cache. I wonder if the panfrost folks can reuse this

Re: [Intel-gfx] [PATCH v3 0/6] Convert the intel iommu driver to the dma-iommu api

2020-09-22 Thread Robin Murphy
On 2020-09-18 21:47, Logan Gunthorpe wrote: Hi Lu, On 2020-09-11 9:21 p.m., Lu Baolu wrote: Tom Murphy has almost done all the work. His latest patch series was posted here. https://lore.kernel.org/linux-iommu/20200903201839.7327-1-murph...@tcd.ie/ Thanks a lot! This series is a follow-up

[PATCHv5 1/6] iommu/io-pgtable-arm: Add support to use system cache

2020-09-22 Thread Sai Prakash Ranjan
Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the attributes set in TCR for the page table walker when using system cache. Signed-off-by: Sai Prakash Ranjan --- drivers/iommu/io-pgtable-arm.c | 7 ++- include/linux/io-pgtable.h | 4 2 files changed, 10 insertions(+), 1

[PATCH v5 5/5] iommu/vt-d: Add is_aux_domain support

2020-09-22 Thread Lu Baolu
With subdevice information opt-in through iommu_ops.aux_at(de)tach_dev() interfaces, the vendor iommu driver is able to learn the knowledge about the relationships between the subdevices and the aux-domains. Implement is_aux_domain() support based on the relationship knowledges. Signed-off-by: Lu

[PATCH v5 4/5] vfio/type1: Use iommu_aux_at(de)tach_group() APIs

2020-09-22 Thread Lu Baolu
Replace iommu_aux_at(de)tach_device() with iommu_at(de)tach_subdev_group(). Signed-off-by: Lu Baolu --- drivers/vfio/vfio_iommu_type1.c | 43 + 1 file changed, 6 insertions(+), 37 deletions(-) diff --git a/drivers/vfio/vfio_iommu_type1.c

[PATCH v5 2/5] iommu: Add iommu_at(de)tach_subdev_group()

2020-09-22 Thread Lu Baolu
This adds two new APIs for the use cases like vfio/mdev where subdevices derived from physical devices are created and put in an iommu_group. The new IOMMU API interfaces mimic the vfio_mdev_at(de)tach_domain() directly, testing whether the resulting device supports IOMMU_DEV_FEAT_AUX and using an

[PATCH v5 0/5] iommu aux-domain APIs extensions

2020-09-22 Thread Lu Baolu
Hi Jorge and Alex, A description of this patch series could be found here. https://lore.kernel.org/linux-iommu/20200901033422.22249-1-baolu...@linux.intel.com/ This version adds some changes according to Alex's review comments. - Add comments and naming rule for subdevices.

[PATCH v5 1/5] iommu: Add optional subdev in aux_at(de)tach ops

2020-09-22 Thread Lu Baolu
In the vfio/mdev use case of aux-domain, the subdevices are created from the physical devices with IOMMU_DEV_FEAT_AUX enabled and the aux-domains are attached to the subdevices through the iommu_ops.aux_attach_dev() interface. Current iommu_ops.aux_at(de)tach_dev() design only takes the

[PATCHv5 6/6] iommu: arm-smmu-impl: Add a space before open parenthesis

2020-09-22 Thread Sai Prakash Ranjan
Fix the checkpatch warning for space required before the open parenthesis. Signed-off-by: Sai Prakash Ranjan --- drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c

[PATCHv5 2/6] iommu/arm-smmu: Add domain attribute for system cache

2020-09-22 Thread Sai Prakash Ranjan
Add iommu domain attribute for using system cache aka last level cache by client drivers like GPU to set right attributes for caching the hardware pagetables into the system cache. Signed-off-by: Sai Prakash Ranjan --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 17 +

[PATCHv5 3/6] drm/msm: rearrange the gpu_rmw() function

2020-09-22 Thread Sai Prakash Ranjan
From: Sharat Masetty The register read-modify-write construct is generic enough that it can be used by other subsystems as needed, create a more generic rmw() function and have the gpu_rmw() use this new function. Signed-off-by: Sharat Masetty Reviewed-by: Jordan Crouse Signed-off-by: Sai

[PATCHv5 5/6] iommu: arm-smmu-impl: Use table to list QCOM implementations

2020-09-22 Thread Sai Prakash Ranjan
Use table and of_match_node() to match qcom implementation instead of multiple of_device_compatible() calls for each QCOM SMMU implementation. Signed-off-by: Sai Prakash Ranjan --- drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 12 1 file changed, 8 insertions(+), 4 deletions(-)

[PATCHv5 4/6] drm/msm/a6xx: Add support for using system cache(LLC)

2020-09-22 Thread Sai Prakash Ranjan
From: Sharat Masetty The last level system cache can be partitioned to 32 different slices of which GPU has two slices preallocated. One slice is used for caching GPU buffers and the other slice is used for caching the GPU SMMU pagetables. This talks to the core system cache driver to acquire

[PATCH 0/1] [PULL REQUEST] iommu/vt-d: patches for v5.10

2020-09-22 Thread Lu Baolu
Hi Joerg, Below patch is ready for v5.10. It includes: - Use device numa domain if RHSA is missing Can you please consider them for v5.10? Best regards, Lu Baolu Lu Baolu (1): iommu/vt-d: Use device numa domain if RHSA is missing drivers/iommu/intel/iommu.c | 37

[PATCH 1/1] iommu/vt-d: Use device numa domain if RHSA is missing

2020-09-22 Thread Lu Baolu
If there are multiple NUMA domains but the RHSA is missing in ACPI/DMAR table, we could default to the device NUMA domain as fall back. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian Cc: Jacob Pan Cc: Kevin Tian Cc: Ashok Raj Link:

[PATCH v5 3/5] iommu: Add iommu_aux_get_domain_for_dev()

2020-09-22 Thread Lu Baolu
The device driver needs an API to get its aux-domain. A typical usage scenario is: unsigned long pasid; struct iommu_domain *domain; struct device *dev = mdev_dev(mdev); struct device *iommu_device = vfio_mdev_get_iommu_device(dev); domain =

[PATCH 3/3] dma-mapping: better document dma_addr_t and DMA_MAPPING_ERROR

2020-09-22 Thread Christoph Hellwig
Move the comment documenting dma_addr_t away from the dma_map_ops definition which isn't very related to it, and toward DMA_MAPPING_ERROR, which is somewhat related. Add a little blurb about DMA_MAPPING_ERROR as well. Signed-off-by: Christoph Hellwig --- include/linux/dma-mapping.h | 16

a few trivial dma-mapping header cleanups

2020-09-22 Thread Christoph Hellwig
Hi all, these three patches clean up dma-mapping.h a little bit ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu

[PATCH 2/3] dma-mapping: move valid_dma_direction to dma-direction.h

2020-09-22 Thread Christoph Hellwig
Move the valid_dma_direction helper to a more suitable header, and clean it up to use the proper enum as well as removing pointless braces. Signed-off-by: Christoph Hellwig --- include/linux/dma-direction.h | 8 +++- include/linux/dma-mapping.h | 7 --- 2 files changed, 7

[PATCH 1/3] dma-mapping: remove DMA_MASK_NONE

2020-09-22 Thread Christoph Hellwig
This value is only used by a PCMCIA driver and not very useful. Signed-off-by: Christoph Hellwig --- drivers/pcmcia/ds.c | 2 +- include/linux/dma-mapping.h | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pcmcia/ds.c b/drivers/pcmcia/ds.c index

RE: [PATCH 3/3] dma-mapping: better document dma_addr_t and DMA_MAPPING_ERROR

2020-09-22 Thread David Laight
From: Christoph Hellwig > Sent: 22 September 2020 14:40 ... > @@ -131,6 +125,16 @@ struct dma_map_ops { > unsigned long (*get_merge_boundary)(struct device *dev); > }; > > +/* > + * A dma_addr_t can hold any valid DMA or bus address for the platform. It > can > + * be given to a device

Re: [PATCH 1/3] dma-mapping: remove DMA_MASK_NONE

2020-09-22 Thread Dominik Brodowski
On Tue, Sep 22, 2020 at 03:40:00PM +0200, Christoph Hellwig wrote: > This value is only used by a PCMCIA driver and not very useful. > > Signed-off-by: Christoph Hellwig Acked-by: Dominik Brodowski ___ iommu mailing list

Re: [PATCH 15/18] dma-mapping: add a new dma_alloc_pages API

2020-09-22 Thread Thomas Bogendoerfer
On Tue, Sep 15, 2020 at 05:51:19PM +0200, Christoph Hellwig wrote: > This API is the equivalent of alloc_pages, except that the returned memory > is guaranteed to be DMA addressable by the passed in device. The > implementation will also be used to provide a more sensible replacement > for

Re: [PATCH 13/18] 53c700: convert to dma_alloc_noncoherent

2020-09-22 Thread Thomas Bogendoerfer
On Tue, Sep 15, 2020 at 05:51:17PM +0200, Christoph Hellwig wrote: > Use the new non-coherent DMA API including proper ownership transfers. > > Signed-off-by: Christoph Hellwig > --- > drivers/scsi/53c700.c | 20 ++-- > 1 file changed, 14 insertions(+), 6 deletions(-)

Re: [PATCH 06/18] lib82596: move DMA allocation into the callers of i82596_probe

2020-09-22 Thread Thomas Bogendoerfer
On Tue, Sep 15, 2020 at 05:51:10PM +0200, Christoph Hellwig wrote: > This allows us to get rid of the LIB82596_DMA_ATTR defined and prepare > for untangling the coherent vs non-coherent DMA allocation API. > > Signed-off-by: Christoph Hellwig > --- > drivers/net/ethernet/i825xx/lasi_82596.c |

Re: [PATCH 14/18] dma-mapping: remove dma_cache_sync

2020-09-22 Thread Thomas Bogendoerfer
On Tue, Sep 15, 2020 at 05:51:18PM +0200, Christoph Hellwig wrote: > All users are gone now, remove the API. > > Signed-off-by: Christoph Hellwig > --- > arch/mips/Kconfig | 1 - > arch/mips/jazz/jazzdma.c| 1 - > arch/mips/mm/dma-noncoherent.c | 6 -- >

Re: [PATCH 11/18] lib82596: convert to dma_alloc_noncoherent

2020-09-22 Thread Thomas Bogendoerfer
On Tue, Sep 15, 2020 at 05:51:15PM +0200, Christoph Hellwig wrote: > Use the new non-coherent DMA API including proper ownership transfers. > This includes moving the DMA helpers to lib82596 based of an ifdef to > avoid include order problems. > > Signed-off-by: Christoph Hellwig > --- >

Re: [PATCH 07/18] 53c700: improve non-coherent DMA handling

2020-09-22 Thread Thomas Bogendoerfer
On Tue, Sep 15, 2020 at 05:51:11PM +0200, Christoph Hellwig wrote: > Switch the 53c700 driver to only use non-coherent descriptor memory if it > really has to because dma_alloc_coherent fails. This doesn't matter for > any of the platforms it runs on currently, but that will change soon. > > To

Re: [PATCH 09/18] sgiwd93: convert to dma_alloc_noncoherent

2020-09-22 Thread Thomas Bogendoerfer
On Tue, Sep 15, 2020 at 05:51:13PM +0200, Christoph Hellwig wrote: > Use the new non-coherent DMA API including proper ownership transfers. > This also means we can allocate the memory as DMA_TO_DEVICE instead > of bidirectional. > > Signed-off-by: Christoph Hellwig > --- >

Re: [PATCH 12/18] sgiseeq: convert to dma_alloc_noncoherent

2020-09-22 Thread Thomas Bogendoerfer
On Tue, Sep 15, 2020 at 05:51:16PM +0200, Christoph Hellwig wrote: > Use the new non-coherent DMA API including proper ownership transfers. > This includes adding additional calls to dma_sync_desc_dev as the > old syncing was rather ad-hoc. > > Thanks to Thomas Bogendoerfer for debugging the

Re: [PATCH 10/18] hal2: convert to dma_alloc_noncoherent

2020-09-22 Thread Thomas Bogendoerfer
On Tue, Sep 15, 2020 at 05:51:14PM +0200, Christoph Hellwig wrote: > Use the new non-coherent DMA API including proper ownership transfers. > This also means we can allocate the buffer memory with the proper > direction instead of bidirectional. > > Signed-off-by: Christoph Hellwig > --- >

Re: [PATCH v3 0/6] Convert the intel iommu driver to the dma-iommu api

2020-09-22 Thread Robin Murphy
On 2020-09-15 09:31, Tvrtko Ursulin wrote: On 15/09/2020 02:47, Lu Baolu wrote: Hi Tvrtko, On 9/14/20 4:04 PM, Tvrtko Ursulin wrote: Hi, On 12/09/2020 04:21, Lu Baolu wrote: Tom Murphy has almost done all the work. His latest patch series was posted here.

[PATCH v2 3/3] arm64: dts: meson: Describe G12b GPU as coherent

2020-09-22 Thread Robin Murphy
According to a downstream commit I found in the Khadas vendor kernel, the GPU on G12b is wired up for ACE-lite, so (now that Panfrost knows how to handle this properly) we should describe it as such. Otherwise the mismatch leads to all manner of fun with mismatched attributes and inadvertently

[PATCH v2 1/3] iommu/io-pgtable-arm: Support coherency for Mali LPAE

2020-09-22 Thread Robin Murphy
Midgard GPUs have ACE-Lite master interfaces which allows systems to integrate them in an I/O-coherent manner. It seems that from the GPU's viewpoint, the rest of the system is its outer shareable domain, and so even when snoop signals are wired up, they are only emitted for outer shareable

[PATCH v2 0/3] drm: panfrost: Coherency support

2020-09-22 Thread Robin Murphy
Hi all, Here's a quick v2 with the tags so far picked up and some inline commentary about the shareability domains for the pagetable code. Robin. Robin Murphy (3): iommu/io-pgtable-arm: Support coherency for Mali LPAE drm/panfrost: Support cache-coherent integrations arm64: dts: meson:

[PATCH v2 2/3] drm/panfrost: Support cache-coherent integrations

2020-09-22 Thread Robin Murphy
When the GPU's ACE-Lite interface is fully wired up and capable of snooping CPU caches, it may be described as "dma-coherent" in devicetree, which will already inform the DMA layer not to perform unnecessary cache maintenance. However, we still need to ensure that the GPU uses the appropriate

[PATCH v10 0/7] IOMMU user API enhancement

2020-09-22 Thread Jacob Pan
IOMMU user API header was introduced to support nested DMA translation and related fault handling. The current UAPI data structures consist of three areas that cover the interactions between host kernel and guest: - fault handling - cache invalidation - bind guest page tables, i.e. guest PASID

Re: [PATCH v9 3/7] iommu/uapi: Introduce enum type for PASID data format

2020-09-22 Thread Jacob Pan
Hi Joerg, I sent out v10 with Randy's comments addressed but I didn't change this patch. Does my explanation below make sense? I am hoping to make it in v5.10 since many other pieces depend on it, your guidance is much appreciated. Jacob On Fri, 18 Sep 2020 10:11:08 -0700, Jacob Pan wrote: >

[PATCH v10 1/7] docs: IOMMU user API

2020-09-22 Thread Jacob Pan
IOMMU UAPI is newly introduced to support communications between guest virtual IOMMU and host IOMMU. There has been lots of discussions on how it should work with VFIO UAPI and userspace in general. This document is intended to clarify the UAPI design and usage. The mechanics of how future

[PATCH v10 6/7] iommu/uapi: Handle data and argsz filled by users

2020-09-22 Thread Jacob Pan
IOMMU user APIs are responsible for processing user data. This patch changes the interface such that user pointers can be passed into IOMMU code directly. Separate kernel APIs without user pointers are introduced for in-kernel users of the UAPI functionality. IOMMU UAPI data has a user filled

[PATCH v10 4/7] iommu/uapi: Use named union for user data

2020-09-22 Thread Jacob Pan
IOMMU UAPI data size is filled by the user space which must be validated by the kernel. To ensure backward compatibility, user data can only be extended by either re-purpose padding bytes or extend the variable sized union at the end. No size change is allowed before the union. Therefore, the

[PATCH v10 5/7] iommu/uapi: Rename uapi functions

2020-09-22 Thread Jacob Pan
User APIs such as iommu_sva_unbind_gpasid() may also be used by the kernel. Since we introduced user pointer to the UAPI functions, in-kernel callers cannot share the same APIs. In-kernel callers are also trusted, there is no need to validate the data. We plan to have two flavors of the same API

[PATCH v10 2/7] iommu/uapi: Add argsz for user filled data

2020-09-22 Thread Jacob Pan
As IOMMU UAPI gets extended, user data size may increase. To support backward compatibiliy, this patch introduces a size field to each UAPI data structures. It is *always* the responsibility for the user to fill in the correct size. Padding fields are adjusted to ensure 8 byte alignment. Specific

[PATCH v10 3/7] iommu/uapi: Introduce enum type for PASID data format

2020-09-22 Thread Jacob Pan
There can be multiple vendor-specific PASID data formats used in UAPI structures. This patch adds enum type with a last entry which makes range checking much easier. Suggested-by: Alex Williamson Reviewed-by: Eric Auger Signed-off-by: Jacob Pan --- include/uapi/linux/iommu.h | 8 ++-- 1

[PATCH v10 7/7] iommu/vt-d: Check UAPI data processed by IOMMU core

2020-09-22 Thread Jacob Pan
IOMMU generic layer already does sanity checks on UAPI data for version match and argsz range based on generic information. This patch adjusts the following data checking responsibilities: - removes the redundant version check from VT-d driver - removes the check for vendor specific data size -

Re: [PATCH v2] iommu/arm: Add module parameter to set msi iova address

2020-09-22 Thread Vennila Megavannan
Sure, that's a great suggestion, I'll rework on the patch and post again. Vennila On 9/21/2020 1:45 PM, Will Deacon wrote: On Mon, Sep 14, 2020 at 11:13:07AM -0700, Vennila Megavannan wrote: From: Srinath Mannam Add provision to change default value of MSI IOVA base to platform's suitable

Re: [PATCH v5 05/38] drm: prime: use sgtable iterators in drm_prime_sg_to_page_addr_arrays()

2020-09-22 Thread Alex Goins
Hi Marek, On Tue, 22 Sep 2020, Marek Szyprowski wrote: > External email: Use caution opening links or attachments > > > Hi Alex, > > On 22.09.2020 01:15, Alex Goins wrote: > > Tested-by: Alex Goins > > > > This change fixes a regression with drm_prime_sg_to_page_addr_arrays() and > > AMDGPU

[PATCH 1/4] iommu/vt-d: Disable SVM in the platform when IOMMUs have inconsistencies

2020-09-22 Thread Kyung Min Park
Some IOMMU Capabilities must be consistent for Shared Virtual Memory (SVM). Audit IOMMU Capability/Extended Capabilities and check if IOMMUs have the consistent value for features as below. When the features are not matched among IOMMUs, disable SVMs in the platform during DMAR initialization.

[PATCH 4/4] iommu/vt-d: Scale capability to the lowest supported between the IOMMUs

2020-09-22 Thread Kyung Min Park
Audit IOMMU Capability/Extended Capabilities and check if the IOMMUs have the consistent value for features as below. Find common denominator for the features and set to the lowest supported value for each IOMMU. Abort hot plug when the hot plugged IOMMU does not meet the aforementioned common

[PATCH 3/4] iommu/vt-d: Audit IOMMUs for Interrupt Remapping features

2020-09-22 Thread Kyung Min Park
Audit IOMMU Capability/Extended Capabilities for Interrupt Remapping. Check if the IOMMUs have the consistent value for the features as below. When the features are not matched among IOMMUs, report out the IOMMU features during irq remapping initialization. Audit IOMMUs again when a device is hot

[PATCH 0/4] Audit Capability and Extended Capability among IOMMUs

2020-09-22 Thread Kyung Min Park
Modern platforms have more than one IOMMU. Each IOMMU has its own feature set. Some of these features must be consistent among IOMMUs. Otherwise, these differences can lead to improper behavior in the system. On the other hand, for some features, each IOMMU can have different capacity values. So,

[PATCH 2/4] iommu/vt-d: Report out when IOMMU features have inconsistencies

2020-09-22 Thread Kyung Min Park
IOMMU features as below can have incompatibilities among IOMMUs. Audit IOMMU Capability/Extended Capability and check if the IOMMUs have the consistent value for features as below. Report out when features as below have incompatibility among IOMMUs. Report out features when below features are

Re: [Intel-gfx] [PATCH v3 0/6] Convert the intel iommu driver to the dma-iommu api

2020-09-22 Thread Logan Gunthorpe
On 2020-09-21 6:24 p.m., Lu Baolu wrote: I'm trying to test this on an old Sandy Bridge, but found that I get spammed with warnings on boot. I've put a sample of a few of them below. They all seem to be related to ioat. I had the same issue with Tom's v2 but never saw

Re: [PATCH v2 0/3] drm: panfrost: Coherency support

2020-09-22 Thread Alyssa Rosenzweig
Series is: Acked-by: Alyssa Rosenzweig On Tue, Sep 22, 2020 at 03:16:47PM +0100, Robin Murphy wrote: > Hi all, > > Here's a quick v2 with the tags so far picked up and some inline > commentary about the shareability domains for the pagetable code. > > Robin. > > > Robin Murphy (3):

[PATCH] Revert "iommu/amd: Treat per-device exclusion ranges as r/w unity-mapped regions"

2020-09-22 Thread Baoquan He
A regression failure of kdump kernel boot was reported on a HPE system. Bisect points at commit 387caf0b759ac43 ("iommu/amd: Treat per-device exclusion ranges as r/w unity-mapped regions") as criminal. Reverting it fix the failure. With the commit, kdump kernel will always print below error

Re: [PATCH] Revert "iommu/amd: Treat per-device exclusion ranges as r/w unity-mapped regions"

2020-09-22 Thread Baoquan He
Forgot CC-ing Jerry, add him. On 09/23/20 at 10:26am, Baoquan He wrote: > A regression failure of kdump kernel boot was reported on a HPE system. > Bisect points at commit 387caf0b759ac43 ("iommu/amd: Treat per-device > exclusion ranges as r/w unity-mapped regions") as criminal. Reverting it >

Re: [PATCH v3 0/6] Convert the intel iommu driver to the dma-iommu api

2020-09-22 Thread Lu Baolu
On 9/22/20 7:05 PM, Robin Murphy wrote: With the previous version of the series I hit a problem on Ivybridge where apparently the dma engine width is not respected. At least that is my layman interpretation of the errors. From the older thread: <3> [209.526605] DMAR: intel_iommu_map: iommu

Re: [PATCH] iommu/qcom: add missing put_device() call in qcom_iommu_of_xlate()

2020-09-22 Thread kernel test robot
Hi Yu, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on iommu/next] [also build test WARNING on linus/master v5.9-rc6 next-20200922] [cannot apply to robclark/msm-next] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting