Hi Ard,
On 2020/10/16 14:54, Ard Biesheuvel wrote:
On Fri, 16 Oct 2020 at 08:51, Hanjun Guo wrote:
On 2020/10/16 2:03, Catalin Marinas wrote:
On Thu, Oct 15, 2020 at 10:26:18PM +0800, Hanjun Guo wrote:
On 2020/10/15 3:12, Nicolas Saenz Julienne wrote:
From: Ard Biesheuvel
We recently
On 2020/10/16 15:27, Hanjun Guo wrote:
The patch only takes the address limit field into account if its value
> 0.
Sorry I missed the if (*->memory_address_limit) check, thanks
for the reminding.
Also, before commit 7fb89e1d44cb6aec ("ACPI/IORT: take _DMA methods
into account for named
On Thu, Oct 15, 2020 at 11:22:11AM -0700, Raj, Ashok wrote:
> Hi Jean
>
> + Baolu who is looking into this.
>
>
> On Thu, Oct 15, 2020 at 11:00:27AM +0200, Jean-Philippe Brucker wrote:
> > Add a parameter to iommu_sva_unbind_device() that tells the IOMMU driver
> > whether the PRI queue needs
On Thu, Oct 15, 2020 at 12:42 AM Christoph Hellwig wrote:
>
> > +phys_addr_t __init of_dma_get_max_cpu_address(struct device_node *np)
> > +{
> > + phys_addr_t max_cpu_addr = PHYS_ADDR_MAX;
> > + struct of_range_parser parser;
> > + phys_addr_t subtree_max_addr;
> > + struct
On 2020-10-16 04:53, Nicolin Chen wrote:
On Thu, Oct 15, 2020 at 10:55:52AM +0100, Robin Murphy wrote:
On 2020-10-15 05:13, Nicolin Chen wrote:
On Wed, Oct 14, 2020 at 06:42:36PM +0100, Robin Murphy wrote:
On 2020-10-09 17:19, Nicolin Chen wrote:
This patch simply adds support for PCI
On Wed, Oct 14, 2020 at 03:16:22AM +, Tian, Kevin wrote:
> Hi, Alex and Jason (G),
>
> How about your opinion for this new proposal? For now looks both
> Jason (W) and Jean are OK with this direction and more discussions
> are possibly required for the new /dev/ioasid interface. Internally
>
On Thu, Oct 15, 2020 at 08:26:54PM +0200, Daniel Kiper wrote:
>
> I am discussing with Ross the other option. We can create
> .rodata.mle_header section and put it at fixed offset as
> kernel_info is. So, we would have, e.g.:
>
> arch/x86/boot/compressed/vmlinux.lds.S:
>
The Qualcomm boot loader configures stream mapping for the peripherals
that it accesses and in particular it sets up the stream mapping for the
display controller to be allowed to scan out a splash screen or EFI
framebuffer.
Read back the stream mappings during initialization and make the
The firmware found in some Qualcomm platforms intercepts writes to the
S2CR register in order to replace the BYPASS type with FAULT. Further
more it treats faults at this level as catastrophic and restarts the
device.
Add support for providing implementation specific versions of the S2CR
write
This is the fourth attempt of inheriting the stream mapping for the framebuffer
on many Qualcomm platforms, in order to not hit catastrophic faults during
arm-smmu initialization.
The new approach does, based on Robin's suggestion, take a much more direct
approach with the allocation of a context
The firmware found in some Qualcomm platforms intercepts writes to S2CR
in order to replace bypass type streams with fault; and ignore S2CR
updates of type fault.
Detect this behavior and implement a custom write_s2cr function in order
to trick the firmware into supporting bypass streams by the
On Fri, Oct 16, 2020 at 03:10:26PM +0100, Robin Murphy wrote:
> On 2020-10-16 04:53, Nicolin Chen wrote:
> > On Thu, Oct 15, 2020 at 10:55:52AM +0100, Robin Murphy wrote:
> > > On 2020-10-15 05:13, Nicolin Chen wrote:
> > > > On Wed, Oct 14, 2020 at 06:42:36PM +0100, Robin Murphy wrote:
> > > > >
On 2020/10/16 2:03, Catalin Marinas wrote:
On Thu, Oct 15, 2020 at 10:26:18PM +0800, Hanjun Guo wrote:
On 2020/10/15 3:12, Nicolas Saenz Julienne wrote:
From: Ard Biesheuvel
We recently introduced a 1 GB sized ZONE_DMA to cater for platforms
incorporating masters that can address less than
On Fri, 16 Oct 2020 at 08:51, Hanjun Guo wrote:
>
> On 2020/10/16 2:03, Catalin Marinas wrote:
> > On Thu, Oct 15, 2020 at 10:26:18PM +0800, Hanjun Guo wrote:
> >> On 2020/10/15 3:12, Nicolas Saenz Julienne wrote:
> >>> From: Ard Biesheuvel
> >>>
> >>> We recently introduced a 1 GB sized
On Thu, 15 Oct 2020 at 12:31, Lorenzo Pieralisi
wrote:
>
> On Wed, Oct 14, 2020 at 09:12:09PM +0200, Nicolas Saenz Julienne wrote:
>
> [...]
>
> > +unsigned int __init acpi_iort_get_zone_dma_size(void)
> > +{
> > + struct acpi_table_iort *iort;
> > + struct acpi_iort_node *node, *end;
> >
On Thu, Oct 15, 2020 at 11:00:29AM +0200, Jean-Philippe Brucker wrote:
> IOMMU drivers only need to flush their PRI queue when faults might be
> pending. According to the PCIe spec (quoted below) this only happens
> when using the "Stop Marker" method. Otherwise the function waits for
> pending
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