[PATCH v3 33/35] iommu/hyper-v: Disable IRQ pseudo-remapping if 15 bit APIC IDs are available

From: David Woodhouse If the 15-bit APIC ID support is present in emulated MSI then there's no need for the pseudo-remapping support. Signed-off-by: David Woodhouse --- drivers/iommu/hyperv-iommu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/hyperv-iommu.c

[PATCH v3 05/35] x86/apic: Cleanup delivery mode defines

From: Thomas Gleixner The enum ioapic_irq_destination_types and the enumerated constants starting with 'dest_' are gross misnomers because they describe the delivery mode. Rename then enum and the constants so they actually make sense. Signed-off-by: Thomas Gleixner Signed-off-by: David

[PATCH v3 22/35] genirq/irqdomain: Implement get_name() method on irqchip fwnodes

From: David Woodhouse Prerequesite to make x86 more irqdomain compliant. Signed-off-by: David Woodhouse Signed-off-by: Thomas Gleixner --- kernel/irq/irqdomain.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c

[PATCH v3 18/35] x86/msi: Remove msidef.h

From: Thomas Gleixner Nothing uses the macro maze anymore. Signed-off-by: Thomas Gleixner Signed-off-by: David Woodhouse --- arch/x86/include/asm/msidef.h | 57 --- 1 file changed, 57 deletions(-) delete mode 100644 arch/x86/include/asm/msidef.h diff --git

[PATCH v3 24/35] iommu/amd: Implement select() method on remapping irqdomain

From: David Woodhouse Preparatory change to remove irq_remapping_get_irq_domain(). Signed-off-by: David Woodhouse Signed-off-by: Thomas Gleixner --- drivers/iommu/amd/iommu.c | 19 +++ 1 file changed, 19 insertions(+) diff --git a/drivers/iommu/amd/iommu.c

[PATCH v3 19/35] x86/io_apic: Cleanup trigger/polarity helpers

From: Thomas Gleixner 'trigger' and 'polarity' are used throughout the I/O-APIC code for handling the trigger type (edge/level) and the active low/high configuration. While there are defines for initializing these variables and struct members, they are not used consequently and the meaning of

[PATCH v3 27/35] x86/hpet: Use irq_find_matching_fwspec() to find remapping irqdomain

From: David Woodhouse All possible parent domains have a select method now. Make use of it. Signed-off-by: David Woodhouse Signed-off-by: Thomas Gleixner --- arch/x86/kernel/hpet.c | 24 ++-- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git

[PATCH v3 08/35] x86/apic: Cleanup destination mode

From: Thomas Gleixner apic::irq_dest_mode is actually a boolean, but defined as u32 and named in a way which does not explain what it means. Make it a boolean and rename it to 'dest_mode_logical' Signed-off-by: Thomas Gleixner Signed-off-by: David Woodhouse --- arch/x86/include/asm/apic.h

[PATCH v3 00/35] Fix x2apic enablement and allow more CPUs, clean up I/OAPIC and MSI bitfields

Fix the conditions for enabling x2apic on guests without interrupt remapping, and support 15-bit Extended Destination ID to allow 32768 CPUs without IR on hypervisors that support it. Make the I/OAPIC code generate its RTE directly from the MSI message created by the parent irqchip, and fix up

[PATCH v3 12/35] x86/msi: Provide msi message shadow structs

From: Thomas Gleixner Create shadow structs with named bitfields for msi_msg data, address_lo and address_hi and use them in the MSI message composer. Provide a function to retrieve the destination ID. This could be inline, but that'd create a circular header dependency. [dwmw2: fix bitfields

[PATCH v3 16/35] x86/kvm: Use msi_msg shadow structs

From: Thomas Gleixner Use the bitfields in the x86 shadow structs instead of decomposing the 32bit value with macros. Signed-off-by: Thomas Gleixner Signed-off-by: David Woodhouse --- arch/x86/kvm/irq_comm.c | 31 +-- 1 file changed, 13 insertions(+), 18

[PATCH v3 30/35] iommu/vt-d: Simplify intel_irq_remapping_select()

From: David Woodhouse Now that the old get_irq_domain() method has gone, consolidate on just the map_XXX_to_iommu() functions. Signed-off-by: David Woodhouse Signed-off-by: Thomas Gleixner --- drivers/iommu/intel/irq_remapping.c | 19 +++ 1 file changed, 7 insertions(+), 12

[PATCH v3 34/35] x86/kvm: Reserve KVM_FEATURE_MSI_EXT_DEST_ID

From: David Woodhouse No functional change; just reserve the feature bit for now so that VMMs can start to implement it. This will allow the host to indicate that MSI emulation supports 15-bit destination IDs, allowing up to 32768 CPUs without interrupt remapping. cf.

[PATCH v3 25/35] iommu/vt-d: Implement select() method on remapping irqdomain

From: David Woodhouse Preparatory for removing irq_remapping_get_irq_domain() Signed-off-by: David Woodhouse Signed-off-by: Thomas Gleixner --- drivers/iommu/intel/irq_remapping.c | 13 + 1 file changed, 13 insertions(+) diff --git a/drivers/iommu/intel/irq_remapping.c

[PATCH v3 26/35] iommu/hyper-v: Implement select() method on remapping irqdomain

From: David Woodhouse Preparatory for removing irq_remapping_get_irq_domain() Signed-off-by: David Woodhouse Signed-off-by: Thomas Gleixner --- drivers/iommu/hyperv-iommu.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/iommu/hyperv-iommu.c

[PATCH v3 10/35] x86/hpet: Move MSI support into hpet.c

From: David Woodhouse This isn't really dependent on PCI MSI; it's just generic MSI which is now supported by the generic x86_vector_domain. Move the HPET MSI support back into hpet.c with the rest of the HPET support. Signed-off-by: David Woodhouse Signed-off-by: Thomas Gleixner ---

[PATCH v3 21/35] x86/ioapic: Generate RTE directly from parent irqchip's MSI message

From: David Woodhouse The I/O-APIC generates an MSI cycle with address/data bits taken from its Redirection Table Entry in some combination which used to make sense, but now is just a bunch of bits which get passed through in some seemingly arbitrary order. Instead of making IRQ remapping

[PATCH v3 20/35] x86/ioapic: Cleanup IO/APIC route entry structs

From: Thomas Gleixner Having two seperate structs for the I/O-APIC RTE entries (non-remapped and DMAR remapped) requires type casts and makes it hard to map. Combine them in IO_APIC_routing_entry by defining a union of two 64bit bitfields. Use naming which reflects which bits are shared and

[PATCH v3 29/35] x86: Kill all traces of irq_remapping_get_irq_domain()

From: David Woodhouse All users are converted to use the fwspec based parent domain lookup. Signed-off-by: David Woodhouse Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/hw_irq.h| 2 -- arch/x86/include/asm/irq_remapping.h | 9 drivers/iommu/amd/iommu.c

[PATCH v3 32/35] x86/apic: Support 15 bits of APIC ID in MSI where available

From: David Woodhouse Some hypervisors can allow the guest to use the Extended Destination ID field in the MSI address to address up to 32768 CPUs. This applies to all downstream devices which generate MSI cycles, including HPET, I/OAPIC and PCI MSI. HPET and PCI MSI use the same

[PATCH v3 01/35] x86/apic: Fix x2apic enablement without interrupt remapping

From: David Woodhouse Currently, Linux as a hypervisor guest will enable x2apic only if there are no CPUs present at boot time with an APIC ID above 255. Hotplugging a CPU later with a higher APIC ID would result in a CPU which cannot be targeted by external interrupts. Add a filter in

[PATCH v3 14/35] iommu/amd: Use msi_msg shadow structs

From: Thomas Gleixner Get rid of the macro mess and use the shadow structs for the x86 specific MSI message format. Convert the intcapxt setup to use named bitfields as well while touching it anyway. Signed-off-by: Thomas Gleixner Signed-off-by: David Woodhouse --- drivers/iommu/amd/init.c

[PATCH v3 07/35] x86/apic: Get rid of apic::dest_logical

From: Thomas Gleixner struct apic has two members which store information about the destination mode: dest_logical and irq_dest_mode. dest_logical contains a mask which was historically used to set the destination mode in IPI messages. Over time the usage was reduced and the logical/physical

[PATCH v3 15/35] PCI: vmd: Use msi_msg shadow structs

From: Thomas Gleixner Use the x86 shadow structs in msi_msg instead of the macros. Signed-off-by: Thomas Gleixner Signed-off-by: David Woodhouse --- drivers/pci/controller/vmd.c | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/vmd.c

[PATCH v3 09/35] x86/apic: Always provide irq_compose_msi_msg() method for vector domain

From: David Woodhouse This shouldn't be dependent on PCI_MSI. HPET and I/O-APIC can deliver interrupts through MSI without having any PCI in the system at all. Signed-off-by: David Woodhouse Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/apic.h | 8 +++-

[PATCH v3 23/35] x86/apic: Add select() method on vector irqdomain

From: David Woodhouse This will be used to select the irqdomain for I/O-APIC and HPET. Signed-off-by: David Woodhouse Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/irqdomain.h | 3 +++ arch/x86/kernel/apic/vector.c| 43 2 files changed, 46

[PATCH v3 04/35] x86/devicetree: Fix the ioapic interrupt type table

From: Thomas Gleixner The ioapic interrupt type table is wrong as it assumes that polarity in IO/APIC context means active high when set. But the IO/APIC polarity is working the other way round. This works because the ordering of the entries is consistent with the device tree and the type

[PATCH v3 02/35] x86/msi: Only use high bits of MSI address for DMAR unit

From: David Woodhouse The Intel IOMMU has an MSI-like configuration for its interrupt, but it isn't really MSI. So it gets to abuse the high 32 bits of the address, and puts the high 24 bits of the extended APIC ID there. This isn't something that can be used in the general case for real MSIs,

[PATCH v3 03/35] x86/apic/uv: Fix inconsistent destination mode

From: Thomas Gleixner The UV x2apic is strictly using physical destination mode, but apic::dest_logical is initialized with APIC_DEST_LOGICAL. This does not matter much because UV does not use any of the generic functions which use apic::dest_logical, but is still inconsistent. Signed-off-by:

[PATCH v3 06/35] x86/apic: Replace pointless apic::dest_logical usage

From: Thomas Gleixner All these functions are only used for logical destination mode. So reading the destination mode mask from the apic structure is a pointless exercise. Just hand in the proper constant: APIC_DEST_LOGICAL. Signed-off-by: Thomas Gleixner Signed-off-by: David Woodhouse ---

[PATCH v3 17/35] x86/pci/xen: Use msi_msg shadow structs

From: Thomas Gleixner Use the msi_msg shadow structs and compose the message with named bitfields instead of the unreadable macro maze. Signed-off-by: Thomas Gleixner Signed-off-by: David Woodhouse --- arch/x86/pci/xen.c | 26 +++--- 1 file changed, 11 insertions(+), 15

[PATCH v3 28/35] x86/ioapic: Use irq_find_matching_fwspec() to find remapping irqdomain

From: David Woodhouse All possible parent domains have a select method now. Make use of it. Signed-off-by: David Woodhouse Signed-off-by: Thomas Gleixner --- arch/x86/kernel/apic/io_apic.c | 25 + 1 file changed, 13 insertions(+), 12 deletions(-) diff --git

[PATCH v3 31/35] x86/ioapic: Handle Extended Destination ID field in RTE

From: David Woodhouse Bits 63-48 of the I/OAPIC Redirection Table Entry map directly to bits 19-4 of the address used in the resulting MSI cycle. Historically, the x86 MSI format only used the top 8 of those 16 bits as the destination APIC ID, and the "Extended Destination ID" in the lower 8

[PATCH v3 11/35] genirq/msi: Allow shadow declarations of msi_msg::$member

From: Thomas Gleixner Architectures like x86 have their MSI messages in various bits of the data, address_lo and address_hi field. Composing or decomposing these messages with bitmasks and shifts is possible, but unreadable gunk. Allow architectures to provide an architecture specific

[PATCH v3 13/35] iommu/intel: Use msi_msg shadow structs

From: Thomas Gleixner Use the bitfields in the x86 shadow struct to compose the MSI message. Signed-off-by: Thomas Gleixner Signed-off-by: David Woodhouse --- drivers/iommu/intel/irq_remapping.c | 24 1 file changed, 16 insertions(+), 8 deletions(-) diff --git

[PATCH v3 35/35] x86/kvm: Enable 15-bit extension when KVM_FEATURE_MSI_EXT_DEST_ID detected

From: David Woodhouse This allows the host to indicate that MSI emulation supports 15-bit destination IDs, allowing up to 32768 CPUs without interrupt remapping. cf. https://patchwork.kernel.org/patch/11816693/ for qemu Signed-off-by: David Woodhouse Acked-by: Paolo Bonzini ---

[GIT PULL] dma-mapping fixes for 5.10

The following changes since commit 270315b8235e3d10c2e360cff56c2f9e0915a252: Merge tag 'riscv-for-linus-5.10-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux (2020-10-19 18:18:30 -0700) are available in the Git repository at:

Re: [GIT PULL] dma-mapping fixes for 5.10

The pull request you sent on Sat, 24 Oct 2020 16:19:35 +0200: > git://git.infradead.org/users/hch/dma-mapping.git tags/dma-mapping-5.10-1 has been merged into torvalds/linux.git: https://git.kernel.org/torvalds/c/1b307ac87075c3207c345822ea276fe4f28481d7 Thank you! -- Deet-doot-dot, I am a

Re: WARNING in dma_map_page_attrs

CC: rdma, looks like rdma from the stack trace On Fri, 23 Oct 2020 20:07:17 -0700 syzbot wrote: > syzbot has found a reproducer for the following issue on: > > HEAD commit:3cb12d27 Merge tag 'net-5.10-rc1' of git://git.kernel.org/.. > git tree: net > console output: