On 2022/6/14 14:49, Tian, Kevin wrote:
From: Lu Baolu
Sent: Tuesday, June 14, 2022 10:51 AM
The disable_dmar_iommu() is called when IOMMU initialization fails or
the IOMMU is hot-removed from the system. In both cases, there is no
need to clear the IOMMU translation data structures for devices.
With the dmabounce removal these aren't used outside of dma-mapping.c,
so mark them static. Move the dma_map_ops declarations down a bit
to avoid lots of forward declarations.
Signed-off-by: Christoph Hellwig
Reviewed-by: Arnd Bergmann
Tested-by: Marc Zyngier
---
From: Arnd Bergmann
The sa platform is one of the two remaining users of the old Arm
specific "dmabounce" code, which is an earlier implementation of the
generic swiotlb.
Linus Walleij submitted a patch that removes dmabounce support from
the ixp4xx, and I had a look at the other user,
virt_to_dma was only used by the now removed dmabounce code.
Signed-off-by: Christoph Hellwig
Reviewed-by: Arnd Bergmann
Tested-by: Marc Zyngier
---
arch/arm/include/asm/dma-direct.h | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git
Use the helpers as expected by the dma-direct code in the old arm
dma-mapping code to ease a gradual switch to the common DMA code.
Signed-off-by: Christoph Hellwig
Reviewed-by: Arnd Bergmann
Tested-by: Marc Zyngier
---
arch/arm/mm/dma-mapping.c | 24
1 file changed,
Only the footbridge platforms provide their own DMA address translation
helpers, so switch to the generic version for all other platforms, and
consolidate the footbridge implementation to remove two levels of
indirection.
Signed-off-by: Christoph Hellwig
Reviewed-by: Arnd Bergmann
Tested-by:
From: Robin Murphy
When an IOMMU is present, we trust that it should be capable
of remapping any physical memory, and since the device masks
represent the input (virtual) addresses to the IOMMU it makes
no sense to validate them against physical PFNs anyway.
Signed-off-by: Robin Murphy
Use dma-direct unconditionally on arm. It has already been used for
some time for LPAE and nommu configurations.
This mostly changes the streaming mapping implementation and the (simple)
coherent allocator for device that are DMA coherent. The existing
complex allocator for uncached mappings
Hi all,
arm is the last platform not using the dma-direct code for directly
mapped DMA. With the dmaboune removal from Arnd we can easily switch
arm to always use dma-direct now (it already does for LPAE configs
and nommu). I'd love to merge this series through the dma-mapping tree
as it gives
Remove the now unused dmabounce code.
Signed-off-by: Christoph Hellwig
Reviewed-by: Arnd Bergmann
---
arch/arm/common/Kconfig| 4 -
arch/arm/common/Makefile | 1 -
arch/arm/common/dmabounce.c| 582 -
arch/arm/include/asm/device.h
From: Robin Murphy
Merge the coherent and non-coherent callbacks down to a single
implementation each, relying on the generic dev->dma_coherent
flag at the points where the difference matters.
Signed-off-by: Robin Murphy
Signed-off-by: Christoph Hellwig
Tested-by: Marc Zyngier
---
From: Robin Murphy
The dma_sync_* operations are now the only difference between the
coherent and non-coherent IOMMU ops. Some minor tweaks to make those
safe for coherent devices with minimal overhead, and we can condense
down to a single set of DMA ops.
Signed-off-by: Robin Murphy
> From: Lu Baolu
> Sent: Tuesday, June 14, 2022 10:52 AM
>
> The iommu->lock is used to protect the per-IOMMU domain ID resource.
> Moving the lock into the ID alloc/free helpers makes the code more
> compact. At the same time, the device_domain_lock is irrelevant to
> the domain ID resource,
> From: Lu Baolu
> Sent: Tuesday, June 14, 2022 10:52 AM
>
> Fold __dmar_remove_one_dev_info() into dmar_remove_one_dev_info()
> which
> is its only caller. Make the spin lock critical range only cover the
> device list change code and remove some unnecessary checks.
>
> Signed-off-by: Lu Baolu
On 2022/6/14 14:52, Tian, Kevin wrote:
From: Lu Baolu
Sent: Tuesday, June 14, 2022 10:52 AM
The iommu->lock is used to protect the per-IOMMU domain ID resource.
Moving the lock into the ID alloc/free helpers makes the code more
compact. At the same time, the device_domain_lock is irrelevant to
On 2022/6/14 15:16, Tian, Kevin wrote:
From: Lu Baolu
Sent: Tuesday, June 14, 2022 10:52 AM
The device_domain_lock is used to protect the device tracking list of
a domain. Remove unnecessary spin_lock/unlock()'s and move the necessary
ones around the list access.
Signed-off-by: Lu Baolu
---
On 2022/6/14 15:19, Tian, Kevin wrote:
From: Baolu Lu
Sent: Tuesday, June 14, 2022 2:13 PM
On 2022/6/14 13:36, Tian, Kevin wrote:
From: Baolu Lu
Sent: Tuesday, June 14, 2022 12:48 PM
On 2022/6/14 12:02, Tian, Kevin wrote:
From: Lu Baolu
Sent: Tuesday, June 14, 2022 11:44 AM
This allows the
Hi all,
after several problems with the current IOMMU mailing list (no DKIM
support, poor b4 interoperability) we have decided to move the IOMMU
development discussions to a new list hosted at lists.linux.dev.
The new list is up and running already, to subscribe please send an
email to
> From: Lu Baolu
> Sent: Tuesday, June 14, 2022 10:51 AM
>
> The domain_translation_struct debugfs node is used to dump the DMAR
> page
> tables for the PCI devices. It potentially races with setting domains to
> devices. The existing code uses a global spinlock device_domain_lock to
> avoid the
> From: Lu Baolu
> Sent: Tuesday, June 14, 2022 10:52 AM
>
> When the IOMMU domain is about to be freed, it should not be set on any
> device. Instead of silently dealing with some bug cases, it's better to
> trigger a warning to report and fix any potential bugs at the first time.
>
>
> From: Lu Baolu
> Sent: Tuesday, June 14, 2022 10:52 AM
>
> The device_domain_lock is used to protect the device tracking list of
> a domain. Remove unnecessary spin_lock/unlock()'s and move the necessary
> ones around the list access.
>
> Signed-off-by: Lu Baolu
> ---
>
On 2022/6/14 13:36, Tian, Kevin wrote:
From: Baolu Lu
Sent: Tuesday, June 14, 2022 12:48 PM
On 2022/6/14 12:02, Tian, Kevin wrote:
From: Lu Baolu
Sent: Tuesday, June 14, 2022 11:44 AM
This allows the upper layers to set a domain to a PASID of a device
if the PASID feature is supported by the
On 2022/6/14 15:07, Tian, Kevin wrote:
From: Lu Baolu
Sent: Tuesday, June 14, 2022 10:52 AM
Fold __dmar_remove_one_dev_info() into dmar_remove_one_dev_info()
which
is its only caller. Make the spin lock critical range only cover the
device list change code and remove some unnecessary checks.
> From: Lu Baolu
> Sent: Tuesday, June 14, 2022 10:51 AM
>
> The disable_dmar_iommu() is called when IOMMU initialization fails or
> the IOMMU is hot-removed from the system. In both cases, there is no
> need to clear the IOMMU translation data structures for devices.
>
> On the initialization
> From: Baolu Lu
> Sent: Tuesday, June 14, 2022 2:13 PM
>
> On 2022/6/14 13:36, Tian, Kevin wrote:
> >> From: Baolu Lu
> >> Sent: Tuesday, June 14, 2022 12:48 PM
> >>
> >> On 2022/6/14 12:02, Tian, Kevin wrote:
> From: Lu Baolu
> Sent: Tuesday, June 14, 2022 11:44 AM
>
> This
On 2022-06-13 15:38, Suthikulpanit, Suravee wrote:
Robin,
On 6/13/2022 4:31 PM, Robin Murphy wrote:
On 2022-06-13 02:25, Suravee Suthikulpanit wrote:
When user requests to change IOMMU domain to a new type, IOMMU generic
layer checks the requested type against the default domain type returned
On Tue, Jun 14, 2022 at 10:21:29AM +0800, Baolu Lu wrote:
> On 2022/6/14 09:54, Jerry Snitselaar wrote:
> > On Mon, Jun 13, 2022 at 6:51 PM Baolu Lu wrote:
> > >
> > > On 2022/6/14 09:44, Jerry Snitselaar wrote:
> > > > On Mon, Jun 13, 2022 at 6:36 PM Baolu Lu
> > > > wrote:
> > > > > On
> Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA. So add
> the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT to let level 1 and level 2
> pgtable support at most 35bit PA.
>
> Signed-off-by: Ning Li
> Signed-off-by: Yunfei Wang
Reviewed-by: Miles Chen
> ---
>
> Rename MTK_IOMMU_TLB_ADDR to MTK_IOMMU_ADDR, and update MTK_IOMMU_ADDR
> definition for better generality.
>
> Signed-off-by: Ning Li
> Signed-off-by: Yunfei Wang
Reviewed-by: Miles Chen
___
iommu mailing list
iommu@lists.linux-foundation.org
On Tue, Jun 14, 2022 at 11:45:35AM -0500, Steve Wahl wrote:
> On Tue, Jun 14, 2022 at 10:21:29AM +0800, Baolu Lu wrote:
> > On 2022/6/14 09:54, Jerry Snitselaar wrote:
> > > On Mon, Jun 13, 2022 at 6:51 PM Baolu Lu wrote:
> > > >
> > > > On 2022/6/14 09:44, Jerry Snitselaar wrote:
> > > > > On
On 09/06/2022 12:08, AngeloGioacchino Del Regno wrote:
Add property "mediatek,pericfg" to let the mtk_iommu driver retrieve
a phandle to the infracfg syscon instead of performing a per-soc
compatible lookup in the entire devicetree and set it as a required
property for MT8195's infra IOMMU.
> From: Lu Baolu
> Sent: Tuesday, June 14, 2022 10:52 AM
>
> The iommu->lock is used to protect changes in root/context/pasid tables
> and domain ID allocation. There's no use case to change these resources
> in any interrupt context. Hence there's no need to disable interrupts
> when helding
Hi Kevin,
Thanks for your reviewing.
On 2022/6/14 14:43, Tian, Kevin wrote:
From: Lu Baolu
Sent: Tuesday, June 14, 2022 10:51 AM
The domain_translation_struct debugfs node is used to dump the DMAR
page
tables for the PCI devices. It potentially races with setting domains to
devices. The
Hi,
For some reason, this series has landed in my spam folder so apologies
for the delay :/
On Sat, Jun 11, 2022 at 06:26:53PM +0800, yf.w...@mediatek.com wrote:
> From: Yunfei Wang
>
> Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA and
> cause pgtable PA size larger than
On 06/06/2022 10:30, John Garry wrote:
Add the IOMMU callback for DMA mapping API dma_opt_mapping_size(), which
allows the drivers to know the optimal mapping limit and thus limit the
requested IOVA lengths.
This value is based on the IOVA rcache range limit, as IOVAs allocated
above this limit
On 09/06/2022 12:07, AngeloGioacchino Del Regno wrote:
This driver will get support for more SoCs and the list of infracfg
compatibles is expected to grow: in order to prevent getting this
situation out of control and see a long list of compatible strings,
add support to retrieve a handle to
On Tue, Jun 14, 2022 at 12:01:45PM -0700, Jerry Snitselaar wrote:
> On Tue, Jun 14, 2022 at 11:45:35AM -0500, Steve Wahl wrote:
> > On Tue, Jun 14, 2022 at 10:21:29AM +0800, Baolu Lu wrote:
> > > On 2022/6/14 09:54, Jerry Snitselaar wrote:
> > > > On Mon, Jun 13, 2022 at 6:51 PM Baolu Lu
> > > >
Hi Kevin,
On Wed, Jun 08, 2022 at 11:48:27PM +, Tian, Kevin wrote:
> > > > The KVM mechanism for controlling wbinvd is only triggered during
> > > > kvm_vfio_group_add(), meaning it is a one-shot test done once the
> > devices
> > > > are setup.
> > >
> > > It's not one-shot.
Robin,
On 6/14/2022 4:51 PM, Robin Murphy wrote:
On 2022-06-13 15:38, Suthikulpanit, Suravee wrote:
Robin,
On 6/13/2022 4:31 PM, Robin Murphy wrote:
Introducing check_domain_type_supported() callback in iommu_ops,
which allows IOMMU generic layer to check with vendor-specific IOMMU driver
Required for turning on per-process page tables for the GPU.
Signed-off-by: Emma Anholt
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index
This is an SMMU for the adreno gpu, and adding this compatible lets
the driver use per-fd page tables, which are required for security
between GPU clients.
Signed-off-by: Emma Anholt
---
Tested with a full deqp-vk run on RB5, which did involve some iommu faults.
On 2022/6/14 14:43, Tian, Kevin wrote:
From: Lu Baolu
Sent: Tuesday, June 14, 2022 10:51 AM
The domain_translation_struct debugfs node is used to dump the DMAR
page
tables for the PCI devices. It potentially races with setting domains to
devices. The existing code uses a global spinlock
On 2022/6/15 05:12, Steve Wahl wrote:
On Tue, Jun 14, 2022 at 12:01:45PM -0700, Jerry Snitselaar wrote:
On Tue, Jun 14, 2022 at 11:45:35AM -0500, Steve Wahl wrote:
On Tue, Jun 14, 2022 at 10:21:29AM +0800, Baolu Lu wrote:
On 2022/6/14 09:54, Jerry Snitselaar wrote:
On Mon, Jun 13, 2022 at
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