Re: [PATCH v3] drm/rockchip: update cursors asynchronously through atomic.

On Mon, 26 Nov 2018 12:36:03 -0800 Eric Anholt wrote: > Michael Zoran writes: > > > On Fri, 2018-11-23 at 11:27 +0900, Tomasz Figa wrote: > >> > >> The point here is not about setting and resetting the plane->fb > >> pointer. It's about what happens inside > >> drm_atomic_set_fb_for_plane().

Re: [PATCH v2 1/5] drm/rockchip: fix fb references in async update

>> On 2019-03-13 4:42 a.m., Tomasz Figa wrote: > >>>>> On Wed, Mar 13, 2019 at 12:52 AM Boris Brezillon > >>>>> wrote: > >>>>>> On Tue, 12 Mar 2019 12:34:45 -0300 > >>>>>> Helen Koike wrote: > &g

[PATCH 0/4] scatterlist: sg_table from virtual pointer

ven if they're not directly impacted by those patches. Let me know if you want me to drop/add people from/to the recipient list. Thanks. Best Regards, Boris [1]http://www.spinics.net/lists/arm-kernel/msg493552.html Boris Brezillon (4): mm: add is_highmem_addr() helper scatterlist: add

[PATCH 1/4] mm: add is_highmem_addr() helper

Add an helper to check if a virtual address is in the highmem region. Signed-off-by: Boris Brezillon --- include/linux/highmem.h | 13 + 1 file changed, 13 insertions(+) diff --git a/include/linux/highmem.h b/include/linux/highmem.h index bb3f329..13dff37 100644 --- a/include/linux

Re: [PATCH 2/4] scatterlist: add sg_alloc_table_from_buf() helper

Hi Russell, On Thu, 31 Mar 2016 15:14:13 +0100 Russell King - ARM Linux wrote: > On Thu, Mar 31, 2016 at 02:29:42PM +0200, Boris Brezillon wrote: > > sg_alloc_table_from_buf() provides an easy solution to create an sg_table > > from a virtual address pointer. This function takes

[PATCH 3/4] spi: use sg_alloc_table_from_buf()

Replace custom implementation of sg_alloc_table_from_buf() by a call to sg_alloc_table_from_buf(). Signed-off-by: Boris Brezillon --- drivers/spi/spi.c | 45 + 1 file changed, 5 insertions(+), 40 deletions(-) diff --git a/drivers/spi/spi.c b/drivers

[PATCH 2/4] scatterlist: add sg_alloc_table_from_buf() helper

sg_alloc_table_from_buf() provides an easy solution to create an sg_table from a virtual address pointer. This function takes care of dealing with vmallocated buffers, buffer alignment, or DMA engine limitations (maximum DMA transfer size). Signed-off-by: Boris Brezillon --- include/linux

[PATCH 4/4] mtd: provide helper to prepare buffers for DMA operations

Some NAND controller drivers are making use of DMA to transfer data from the controller to the buffer passed by the MTD user. Provide a generic mtd_map/unmap_buf() implementation to avoid open coded (and sometime erroneous) implementations. Signed-off-by: Boris Brezillon --- drivers/mtd

Re: [PATCH 1/4] mm: add is_highmem_addr() helper

On Mon, 4 Apr 2016 13:44:11 +0530 Vignesh R wrote: > Hi, > > On 03/31/2016 05:59 PM, Boris Brezillon wrote: > > Add an helper to check if a virtual address is in the highmem region. > > > > Signed-off-by: Boris Brezillon > > --- > > include/linux/h

Re: [PATCH v2 14/21] mtd: Remove depends on HAS_DMA in case of platform dependency

a/drivers/mtd/spi-nor/Kconfig > +++ b/drivers/mtd/spi-nor/Kconfig > @@ -71,7 +71,7 @@ config SPI_FSL_QUADSPI > config SPI_HISI_SFC > tristate "Hisilicon SPI-NOR Flash Controller(SFC)" > depends on ARCH_HISI || COMPILE_TEST > - depends on HAS_IOMEM &

Re: [PATCH 3/3] arm64: dts: meson: Describe G12b GPU as coherent

Hi Robin, Neil, On Wed, 16 Sep 2020 10:26:43 +0200 Neil Armstrong wrote: > Hi Robin, > > On 16/09/2020 01:51, Robin Murphy wrote: > > According to a downstream commit I found in the Khadas vendor kernel, > > the GPU on G12b is wired up for ACE-lite, so (now that Panfrost knows > > how to handle

Re: [PATCH 3/3] arm64: dts: meson: Describe G12b GPU as coherent

On Mon, 5 Oct 2020 09:34:06 +0100 Steven Price wrote: > On 05/10/2020 09:15, Boris Brezillon wrote: > > Hi Robin, Neil, > > > > On Wed, 16 Sep 2020 10:26:43 +0200 > > Neil Armstrong wrote: > > > >> Hi Robin, > >> > >> On

Re: [PATCH v2 1/3] iommu/io-pgtable-arm: Support coherency for Mali LPAE

On Tue, 22 Sep 2020 15:16:48 +0100 Robin Murphy wrote: > Midgard GPUs have ACE-Lite master interfaces which allows systems to > integrate them in an I/O-coherent manner. It seems that from the GPU's > viewpoint, the rest of the system is its outer shareable domain, and so > even when snoop signal

Re: [PATCH v2 1/3] iommu/io-pgtable-arm: Support coherency for Mali LPAE

On Mon, 5 Oct 2020 16:16:32 +0100 Steven Price wrote: > On 05/10/2020 15:50, Boris Brezillon wrote: > > On Tue, 22 Sep 2020 15:16:48 +0100 > > Robin Murphy wrote: > > > >> Midgard GPUs have ACE-Lite master interfaces which allows systems to > >> integ

[PATCH v2 0/5] drm/panfrost: Add extra GPU-usage flags

a new IOMMU_ flag is the right solution, but IOMMU_CACHE doesn't feel like a good fit either. Please let me know if you have better ideas. Regards, Boris [1]https://patchwork.kernel.org/project/dri-devel/patch/20210930184723.1482426-1-boris.brezil...@collabora.com/ Boris Brezillon (5):

[PATCH v2 1/5] [RFC]iommu: Add a IOMMU_DEVONLY protection flag

used by the ARM MMU driver to flag Mali mappings accessed only by the GPU as Inner-shareable. Signed-off-by: Boris Brezillon --- include/linux/iommu.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index d2f3435e7d17..db14781b522f 100644

[PATCH v2 2/5] [RFC]iommu/io-pgtable-arm: Take the DEVONLY flag into account on ARM_MALI_LPAE

Restrict the shareability domain when mapping buffers that are GPU-visible only. Signed-off-by: Boris Brezillon --- Flagged RFC because I'm not sure adding a new flag is the right way to convey the 'dev-private buffer' information. --- drivers/iommu/io-pgt

[PATCH v2 3/5] drm/panfrost: Add PANFROST_BO_NO{READ,WRITE} flags

So we can create GPU mappings without R/W permissions. Particularly useful to debug corruptions caused by out-of-bound writes. Signed-off-by: Boris Brezillon --- drivers/gpu/drm/panfrost/panfrost_drv.c | 11 ++- drivers/gpu/drm/panfrost/panfrost_gem.c | 2 ++ drivers/gpu/drm/panfrost

[PATCH v2 5/5] drm/panfrost: Bump the driver version to 1.3

Bump the driver version to 1.3 to account for the PANFROST_BO_NO{READ,WRITE,GPUONLY} flags addition. Signed-off-by: Boris Brezillon --- drivers/gpu/drm/panfrost/panfrost_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b

[PATCH v2 4/5] drm/panfrost: Add a PANFROST_BO_GPUONLY flag

This lets the driver reduce shareability domain of the MMU mapping, which can in turn reduce access time and save power on cache-coherent systems. Signed-off-by: Boris Brezillon --- drivers/gpu/drm/panfrost/panfrost_drv.c | 3 ++- drivers/gpu/drm/panfrost/panfrost_gem.c | 1 + drivers/gpu/drm

Re: [PATCH v2 3/5] drm/panfrost: Add PANFROST_BO_NO{READ,WRITE} flags

On Fri, 1 Oct 2021 16:34:25 +0200 Boris Brezillon wrote: > So we can create GPU mappings without R/W permissions. Particularly > useful to debug corruptions caused by out-of-bound writes. > > Signed-off-by: Boris Brezillon Oops, forgot: Reviewed-by: Alyssa Rosenzweig Reviewe

Re: [PATCH v2 4/5] drm/panfrost: Add a PANFROST_BO_GPUONLY flag

On Fri, 1 Oct 2021 16:13:42 +0100 Steven Price wrote: > On 01/10/2021 15:34, Boris Brezillon wrote: > > This lets the driver reduce shareability domain of the MMU mapping, > > which can in turn reduce access time and save power on cache-coherent > > systems. > >

Re: [PATCH v2 1/5] [RFC]iommu: Add a IOMMU_DEVONLY protection flag

Hello Joerg, On Mon, 18 Oct 2021 12:25:38 +0200 Joerg Roedel wrote: > On Fri, Oct 01, 2021 at 04:34:23PM +0200, Boris Brezillon wrote: > > +/* > > + * Mapping is only accessed by the device behind the iommu. That means > > other > > + * devices or CPUs are not expec

Re: [PATCH v3 14/20] mtd: Remove depends on HAS_DMA in case of platform dependency

On Tue, 17 Apr 2018 19:49:14 +0200 Geert Uytterhoeven wrote: > Remove dependencies on HAS_DMA where a Kconfig symbol depends on another > symbol that implies HAS_DMA, and, optionally, on "|| COMPILE_TEST". > In most cases this other symbol is an architecture or platform specific > symbol, or PCI.