[PATCH] driver/iommu/intel_irq_remapping: Print x2apic opt out info instead of printing a warning

2015-02-21 Thread Fenghua Yu
From: Fenghua Yu fenghua...@intel.com BIOS can set up x2apic_opt_out bit on some platforms. This is not a BIOS problem. A user can either disable the x2apic_opt_out bit in BIOS or by kernel parameter no_x2apic_optout. Instead of printing a warning, we just print information of x2apic opt out

Re: [PATCH 0/2] iommu: Remove iommu_sva_ops::mm_exit()

2020-04-08 Thread Fenghua Yu
On Wed, Apr 08, 2020 at 07:32:18PM -0300, Jason Gunthorpe wrote: > On Wed, Apr 08, 2020 at 02:35:52PM -0700, Jacob Pan wrote: > > > On Wed, Apr 08, 2020 at 11:35:52AM -0700, Jacob Pan wrote: > > > > Hi Jean, > > > > > > > > On Wed, 8 Apr 2020 16:04:25 +0200 > > > > Jean-Philippe Brucker wrote:

Re: [PATCH v5 02/25] iommu/sva: Manage process address spaces

2020-04-20 Thread Fenghua Yu
On Mon, Apr 20, 2020 at 10:48:50AM -0700, Jacob Pan wrote: > On Mon, 20 Apr 2020 10:57:27 -0300 > Jason Gunthorpe wrote: > > > On Mon, Apr 20, 2020 at 09:42:13AM +0200, Jean-Philippe Brucker wrote: > > > On Thu, Apr 16, 2020 at 05:13:31AM -0700, Christoph Hellwig wrote: > > > > On Thu, Apr 16,

[PATCH 1/7] docs: x86: Add a documentation for ENQCMD

2020-03-30 Thread Fenghua Yu
From: Ashok Raj ENQCMD and Data Streaming Accelerator (DSA) and all of their associated features are a complicated stack with lots of interconnected pieces. This documentation provides a big picture overview for all of the features. Signed-off-by: Ashok Raj Co-developed-by: Fenghua Yu Signed

[PATCH 7/7] x86/process: Clear PASID state for a newly forked/cloned thread

2020-03-30 Thread Fenghua Yu
s Gleixner Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- arch/x86/kernel/process.c | 13 + 1 file changed, 13 insertions(+) diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 87de18c64cf5..cefdc8f7fc13 100644 --- a/arch/x86/kernel/process.c +++ b/arch/

[PATCH 4/7] x86/msr-index: Define IA32_PASID MSR

2020-03-30 Thread Fenghua Yu
-by: Fenghua Yu Reviewed-by: Tony Luck --- arch/x86/include/asm/msr-index.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index d5e517d1c3dd..ebda24839dc5 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm

[PATCH 0/7] x86: tag application address space for devices

2020-03-30 Thread Fenghua Yu
-streaming-accelerator-preliminary-architecture-specification Ashok Raj (1): docs: x86: Add a documentation for ENQCMD Fenghua Yu (5): x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions x86/msr-index: Define IA32_PASID MSR x86/mmu: Allocate/free PASID x86/traps: Fix up invalid

[PATCH 3/7] x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature

2020-03-30 Thread Fenghua Yu
From: Yu-cheng Yu The IA32_PASID MSR is used when a task submits work via the ENQCMD instruction. The per task MSR is stored in the task's supervisor FPU PASID state and is context switched by XSAVES/XRSTORS. Signed-off-by: Yu-cheng Yu Co-developed-by: Fenghua Yu Signed-off-by: Fenghua Yu

[PATCH 5/7] x86/mmu: Allocate/free PASID

2020-03-30 Thread Fenghua Yu
ce atatches (whether to the same device or another SVM device) will re-use the same PASID. The PASID is freed when the process exits (so no need to keep reference counts on how many SVM devices are sharing the PASID). Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- arch/x86/include/asm/iommu.

[PATCH 6/7] x86/traps: Fix up invalid PASID

2020-03-30 Thread Fenghua Yu
will be repeated and we will hit case "2". Suggested-by: Thomas Gleixner Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- arch/x86/include/asm/iommu.h | 1 + arch/x86/kernel/traps.c | 17 + drivers/iommu/intel-svm.c| 37 +

[PATCH 2/7] x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions

2020-03-30 Thread Fenghua Yu
in the series and in device drivers. The CPU feature flag is shown as "enqcmd" in /proc/cpuinfo. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x

Re: [PATCH 1/7] docs: x86: Add a documentation for ENQCMD

2020-04-27 Thread Fenghua Yu
On Sun, Apr 26, 2020 at 01:02:12PM +0200, Thomas Gleixner wrote: > Fenghua Yu writes: > > s/Add a documentation/Add documentation/ > > > From: Ashok Raj > > > > ENQCMD and Data Streaming Accelerator (DSA) and all of their associated > > featur

Re: [PATCH 6/7] x86/traps: Fix up invalid PASID

2020-04-27 Thread Fenghua Yu
On Sun, Apr 26, 2020 at 05:25:06PM +0200, Thomas Gleixner wrote: > Fenghua Yu writes: > > A #GP fault is generated when ENQCMD instruction is executed without > > a valid PASID value programmed in. > > Programmed in what? Will change to "...programmed in the PASID M

Re: [PATCH 3/7] x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature

2020-04-27 Thread Fenghua Yu
On Sun, Apr 26, 2020 at 01:17:11PM +0200, Thomas Gleixner wrote: > Fenghua Yu writes: > > From: Yu-cheng Yu > > > > The IA32_PASID MSR is used when a task submits work via the ENQCMD > > instruction. > > Is used? > > > The per task MSR is stored in t

Re: [PATCH 4/7] x86/msr-index: Define IA32_PASID MSR

2020-04-27 Thread Fenghua Yu
On Sun, Apr 26, 2020 at 01:22:00PM +0200, Thomas Gleixner wrote: > Fenghua Yu writes: > > > The IA32_PASID MSR (0xd93) contains the Process Address Space Identifier > > (PASID), a 20-bit value. Bit 31 must be set to indicate the value > > programmed in the MSR is va

Re: [PATCH 2/7] x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions

2020-04-27 Thread Fenghua Yu
On Sun, Apr 26, 2020 at 01:06:33PM +0200, Thomas Gleixner wrote: > Fenghua Yu writes: > > A user space application can execute ENQCMD instruction to submit work > > to device. The kernel executes ENQCMDS instruction to submit work to > > device. > > So a user spac

Re: [PATCH 5/7] x86/mmu: Allocate/free PASID

2020-04-28 Thread Fenghua Yu
On Sun, Apr 26, 2020 at 04:55:25PM +0200, Thomas Gleixner wrote: > Fenghua Yu writes: > > diff --git a/arch/x86/include/asm/mmu.h b/arch/x86/include/asm/mmu.h > > index bdeae9291e5c..137bf51f19e6 100644 > > --- a/arch/x86/include/asm/mmu.h > > +++ b/arch/x86/include/as

Re: [PATCH 5/7] x86/mmu: Allocate/free PASID

2020-04-27 Thread Fenghua Yu
On Sun, Apr 26, 2020 at 04:55:25PM +0200, Thomas Gleixner wrote: > Fenghua Yu writes: > > +++ b/arch/x86/include/asm/mmu.h @@ -50,6 +50,10 @@ typedef struct { > > u16 pkey_allocation_map; s16 execute_only_pkey; > > #endif > > + +#ifdef CONFIG_INTEL_IOMMU_SVM +

Re: [PATCH 0/7] x86: tag application address space for devices

2020-04-22 Thread Fenghua Yu
On Mon, Mar 30, 2020 at 12:33:01PM -0700, Fenghua Yu wrote: > Typical hardware devices require a driver stack to translate application > buffers to hardware addresses, and a kernel-user transition to notify the > hardware of new work. What if both the translation and transition overhea

Re: [PATCH v7 9/9] x86/mmu: Allocate/free PASID

2020-09-03 Thread Fenghua Yu
Hi, Thomas, Andy, et al, On Thu, Aug 27, 2020 at 08:06:34AM -0700, Fenghua Yu wrote: > A PASID is allocated for an "mm" the first time any thread binds > to an SVM capable device and is freed from the "mm" when the SVM is > unbound by the last thread. It's possible f

[PATCH v8 9/9] x86/mmu: Allocate/free PASID

2020-09-15 Thread Fenghua Yu
mm's PASID (non-zero for valid PASID or 0 for invalid PASID) is propagated to per-thread PASID MSR for all threads within the mm through IPI, context switch, or inherit. So that a running thread has the right PASID MSR matching the mm's PASID. Suggested-by: Andy Lutomirski Signed-off-by: Feng

[PATCH v8 7/9] mm: Define pasid in mm

2020-09-15 Thread Fenghua Yu
PASID is shared by all threads in a process. So the logical place to keep track of it is in the "mm". Both ARM and X86 need to use the PASID in the "mm". Suggested-by: Christoph Hellwig Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v4: - Change PASID type to

[PATCH v8 1/9] drm, iommu: Change type of pasid to u32

2020-09-15 Thread Fenghua Yu
xplicit than "unsigned int". No PASID type change in uapi although it defines PASID as __u64 in some places. Suggested-by: Thomas Gleixner Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck Reviewed-by: Lu Baolu Acked-by: Felix Kuehling --- v8: - Change subject to "drm, iommu:..

[PATCH v8 5/9] x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature

2020-09-15 Thread Fenghua Yu
From: Yu-cheng Yu ENQCMD instruction reads PASID from IA32_PASID MSR. The MSR is stored in the task's supervisor FPU PASID state and is context switched by XSAVES/XRSTORS. Signed-off-by: Yu-cheng Yu Co-developed-by: Fenghua Yu Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2

[PATCH v8 0/9] x86: tag application address space for devices

2020-09-15 Thread Fenghua Yu
nsistently (Thomas) (these 3 patches could be in a separate patch set) - Add patch 8 to move "pasid" to generic mm_struct (Christoph). Jean-Philippe Brucker released a virtually same patch. Upstream only needs one of the two. - Add patch 9 to initialize PASID in a new mm. - Plus oth

[PATCH v8 4/9] x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions

2020-09-15 Thread Fenghua Yu
in ENQCMDS. There isn't any usage of ENQCMD in the kernel as of now. The CPU feature flag is shown as "enqcmd" in /proc/cpuinfo. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Re-write commit message (Thomas) arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cp

[PATCH v8 8/9] x86/cpufeatures: Mark ENQCMD as disabled when configured out

2020-09-15 Thread Fenghua Yu
Currently, the ENQCMD feature depends on CONFIG_IOMMU_SUPPORT. Add X86_FEATURE_ENQCMD to the disabled features mask. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v8: - Re-write commit message (Boris). - Move "#ifdef CONFIG_IOMMU_SUPPORT" hunk from patch 9 (Boris). v

[PATCH v8 6/9] x86/msr-index: Define IA32_PASID MSR

2020-09-15 Thread Fenghua Yu
The IA32_PASID MSR (0xd93) contains the Process Address Space Identifier (PASID), a 20-bit value. Bit 31 must be set to indicate the value programmed in the MSR is valid. Hardware uses PASID to identify process address space and direct responses to the right address space. Signed-off-by: Fenghua

[PATCH v8 2/9] iommu/vt-d: Change flags type to unsigned int in binding mm

2020-09-15 Thread Fenghua Yu
"flags" passed to intel_svm_bind_mm() is a bit mask and should be defined as "unsigned int" instead of "int". Change its type to "unsigned int". Suggested-by: Thomas Gleixner Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck Reviewed-by: Lu Baolu -

[PATCH v8 3/9] Documentation/x86: Add documentation for SVA (Shared Virtual Addressing)

2020-09-15 Thread Fenghua Yu
From: Ashok Raj ENQCMD and Data Streaming Accelerator (DSA) and all of their associated features are a complicated stack with lots of interconnected pieces. This documentation provides a big picture overview for all of the features. Signed-off-by: Ashok Raj Co-developed-by: Fenghua Yu Signed

Re: [PATCH v7 9/9] x86/mmu: Allocate/free PASID

2020-09-14 Thread Fenghua Yu
Hi, Boris, On Mon, Sep 07, 2020 at 01:18:43PM +0200, Borislav Petkov wrote: > On Thu, Aug 27, 2020 at 08:06:34AM -0700, Fenghua Yu wrote: > > +*/ > > + xsave = >state.xsave; > > + xsave->header.xfeatures |= XFEATURE_MASK_PASID; &

Re: [PATCH v7 1/9] iommu: Change type of pasid to u32

2020-09-04 Thread Fenghua Yu
drm, iommu: Change type ... > > > On Thu, Aug 27, 2020 at 08:06:26AM -0700, Fenghua Yu wrote: > > PASID is defined as a few different types in iommu including "int", > > "u32", and "unsigned int". To be consistent and to match with uapi &

Re: [PATCH v7 1/9] iommu: Change type of pasid to u32

2020-09-04 Thread Fenghua Yu
Hi, Boris, On Fri, Sep 04, 2020 at 09:45:19PM +0200, Borislav Petkov wrote: > On Fri, Sep 04, 2020 at 04:06:13PM +0000, Fenghua Yu wrote: > > Thank you very much for your review! > > I'm not done with my review yet. > > > Could you please consider to commit the series

[PATCH v7 3/9] docs: x86: Add documentation for SVA (Shared Virtual Addressing)

2020-08-27 Thread Fenghua Yu
From: Ashok Raj ENQCMD and Data Streaming Accelerator (DSA) and all of their associated features are a complicated stack with lots of interconnected pieces. This documentation provides a big picture overview for all of the features. Signed-off-by: Ashok Raj Co-developed-by: Fenghua Yu Signed

[PATCH v7 0/9] x86: tag application address space for devices

2020-08-27 Thread Fenghua Yu
rucker released a virtually same patch. Upstream only needs one of the two. - Add patch 9 to initialize PASID in a new mm. - Plus other changes described in each patch (Thomas) Ashok Raj (1): docs: x86: Add documentation for SVA (Shared Virtual Addressing) Fenghua Yu (7): iommu: Change type of

[PATCH v7 6/9] x86/msr-index: Define IA32_PASID MSR

2020-08-27 Thread Fenghua Yu
The IA32_PASID MSR (0xd93) contains the Process Address Space Identifier (PASID), a 20-bit value. Bit 31 must be set to indicate the value programmed in the MSR is valid. Hardware uses PASID to identify process address space and direct responses to the right address space. Signed-off-by: Fenghua

[PATCH v7 7/9] mm: Define pasid in mm

2020-08-27 Thread Fenghua Yu
PASID is shared by all threads in a process. So the logical place to keep track of it is in the "mm". Both ARM and X86 need to use the PASID in the "mm". Suggested-by: Christoph Hellwig Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v4: - Change PASID type to

[PATCH v7 5/9] x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature

2020-08-27 Thread Fenghua Yu
From: Yu-cheng Yu ENQCMD instruction reads PASID from IA32_PASID MSR. The MSR is stored in the task's supervisor FPU PASID state and is context switched by XSAVES/XRSTORS. Signed-off-by: Yu-cheng Yu Co-developed-by: Fenghua Yu Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2

[PATCH v7 8/9] x86/cpufeatures: Mark ENQCMD as disabled when configured out

2020-08-27 Thread Fenghua Yu
Currently the ENQCMD feature cannot be used if CONFIG_INTEL_IOMMU_SVM is not set. Add X86_FEATURE_ENQCMD to the disabled features mask. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v7: - Split this patch from a previous patch. arch/x86/include/asm/disabled-features.h | 9 - 1

[PATCH v7 4/9] x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions

2020-08-27 Thread Fenghua Yu
in ENQCMDS. There isn't any usage of ENQCMD in the kernel as of now. The CPU feature flag is shown as "enqcmd" in /proc/cpuinfo. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Re-write commit message (Thomas) arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cp

[PATCH v7 2/9] iommu/vt-d: Change flags type to unsigned int in binding mm

2020-08-27 Thread Fenghua Yu
"flags" passed to intel_svm_bind_mm() is a bit mask and should be defined as "unsigned int" instead of "int". Change its type to "unsigned int". Suggested-by: Thomas Gleixner Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck Reviewed-by: Lu Baolu -

[PATCH v7 9/9] x86/mmu: Allocate/free PASID

2020-08-27 Thread Fenghua Yu
mm's PASID (non-zero for valid PASID or 0 for invalid PASID) is propagated to per-thread PASID MSR for all threads within the mm through through IPI, context switch, or inherit to ensure a running thread has the right PASID MSR matching the mm's PASID. Suggested-by: Andy Lutomirski Signed-off-by:

[PATCH v7 1/9] iommu: Change type of pasid to u32

2020-08-27 Thread Fenghua Yu
xplicit than "unsigned int". No PASID type change in uapi although it defines PASID as __u64 in some places. Suggested-by: Thomas Gleixner Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck Reviewed-by: Lu Baolu Acked-by: Felix Kuehling --- v7: - Add "Acked-by: Felix Kuehling &qu

Re: [PATCH v8 0/9] x86: tag application address space for devices

2020-09-17 Thread Fenghua Yu
Hi, Joerg, On Wed, Sep 16, 2020 at 10:06:02AM +0200, Joerg Roedel wrote: > On Tue, Sep 15, 2020 at 09:30:04AM -0700, Fenghua Yu wrote: > > Ashok Raj (1): > > Documentation/x86: Add documentation for SVA (Shared Virtual > > Addressing) > > > > Fenghua Yu (

Re: [PATCH v10 01/13] mm: Define pasid in mm

2020-09-28 Thread Fenghua Yu
Hi, Will and Jean, On Mon, Sep 28, 2020 at 11:22:51PM +0100, Will Deacon wrote: > On Fri, Sep 18, 2020 at 12:18:41PM +0200, Jean-Philippe Brucker wrote: > > From: Fenghua Yu > > > > PASID is shared by all threads in a process. So the logical place to keep > > track

Re: [PATCH v7 3/9] docs: x86: Add documentation for SVA (Shared Virtual Addressing)

2020-09-14 Thread Fenghua Yu
Hi, Randy, On Sat, Sep 05, 2020 at 10:54:59AM -0700, Randy Dunlap wrote: > Hi, > > I'll add a few edits other than those that Borislav made. > (nice review job, BP) > > > On 8/27/20 8:06 AM, Fenghua Yu wrote: > > From: Ashok Raj > > > > ENQCMD and D

Re: [PATCH v8 3/9] Documentation/x86: Add documentation for SVA (Shared Virtual Addressing)

2020-09-18 Thread Fenghua Yu
On Thu, Sep 17, 2020 at 07:30:41PM +0200, Borislav Petkov wrote: > On Thu, Sep 17, 2020 at 10:22:39AM -0700, Raj, Ashok wrote: > > s/translation again/translation > > Ok, last one. Now stop looking at that text because you'll find more. > > :-))) Thank you very much for taking care of the

Re: [PATCH v6 12/12] x86/traps: Fix up invalid PASID

2020-08-03 Thread Fenghua Yu
Hi, Andy, On Fri, Jul 31, 2020 at 06:28:37PM -0700, Andy Lutomirski wrote: > On Mon, Jul 13, 2020 at 4:48 PM Fenghua Yu wrote: > > > > A #GP fault is generated when ENQCMD instruction is executed without > > a valid PASID value programmed in the current thread's PASID M

Re: [PATCH v6 12/12] x86/traps: Fix up invalid PASID

2020-07-31 Thread Fenghua Yu
Hi, Andy, On Fri, Jul 31, 2020 at 04:34:11PM -0700, Andy Lutomirski wrote: > On Mon, Jul 13, 2020 at 4:48 PM Fenghua Yu wrote: > > > > A #GP fault is generated when ENQCMD instruction is executed without > > a valid PASID value programmed in the current thread's PASID M

Re: [PATCH v5 01/12] iommu: Change type of pasid to u32

2020-07-02 Thread Fenghua Yu
Hi, Felix, Thomas, Joerg and maintainers, On Tue, Jun 30, 2020 at 10:12:38PM -0400, Felix Kuehling wrote: > Am 2020-06-30 um 7:44 p.m. schrieb Fenghua Yu: > You didn't change the return types of amdgpu_pasid_alloc and > kfd_pasid_alloc. amdgpu_pasid_alloc returns int, because it c

Re: [PATCH v5 00/12] x86: tag application address space for devices

2020-07-07 Thread Fenghua Yu
Hi, Thomas, Joerg, Boris, Ingo, Baolu, and x86/iommu maintainers, On Tue, Jun 30, 2020 at 04:44:30PM -0700, Fenghua Yu wrote: > Typical hardware devices require a driver stack to translate application > buffers to hardware addresses, and a kernel-user transition to notify the > hardwa

[PATCH v6 02/12] iommu/vt-d: Change flags type to unsigned int in binding mm

2020-07-13 Thread Fenghua Yu
"flags" passed to intel_svm_bind_mm() is a bit mask and should be defined as "unsigned int" instead of "int". Change its type to "unsigned int". Suggested-by: Thomas Gleixner Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck Reviewed-by: Lu Baolu -

[PATCH v6 08/12] fork: Clear PASID for new mm

2020-07-13 Thread Fenghua Yu
When a new mm is created, its PASID should be cleared, i.e. the PASID is initialized to its init state 0 on both ARM and X86. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Add this patch to initialize PASID value for a new mm. include/linux/mm_types.h | 2 ++ kernel/fork.c

[PATCH v6 01/12] iommu: Change type of pasid to u32

2020-07-13 Thread Fenghua Yu
xplicit than "unsigned int". No PASID type change in uapi although it defines PASID as __u64 in some places. Suggested-by: Thomas Gleixner Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck Reviewed-by: Lu Baolu Acked-by: Felix Kuehling --- v6: - Change return type to u32 for kfd_pas

[PATCH v6 05/12] x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature

2020-07-13 Thread Fenghua Yu
From: Yu-cheng Yu ENQCMD instruction reads PASID from IA32_PASID MSR. The MSR is stored in the task's supervisor FPU PASID state and is context switched by XSAVES/XRSTORS. Signed-off-by: Yu-cheng Yu Co-developed-by: Fenghua Yu Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2

[PATCH v6 10/12] x86/mmu: Allocate/free PASID

2020-07-13 Thread Fenghua Yu
w many SVM devices are sharing the PASID). Currently the ENQCMD feature cannot be used if CONFIG_INTEL_IOMMU_SVM is not set. Add X86_FEATURE_ENQCMD to the disabled features mask as appropriate and use cpu_feature_enabled() to check the feature. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck Revie

[PATCH v6 09/12] x86/process: Clear PASID state for a newly forked/cloned thread

2020-07-13 Thread Fenghua Yu
s Gleixner Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Modify init_task_pasid(). arch/x86/kernel/process.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index f362ce0d5ac0..1b1492e337a6 100644 --- a/arch/

[PATCH v6 03/12] docs: x86: Add documentation for SVA (Shared Virtual Addressing)

2020-07-13 Thread Fenghua Yu
From: Ashok Raj ENQCMD and Data Streaming Accelerator (DSA) and all of their associated features are a complicated stack with lots of interconnected pieces. This documentation provides a big picture overview for all of the features. Signed-off-by: Ashok Raj Co-developed-by: Fenghua Yu Signed

[PATCH v6 04/12] x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions

2020-07-13 Thread Fenghua Yu
in ENQCMDS. There isn't any usage of ENQCMD in the kernel as of now. The CPU feature flag is shown as "enqcmd" in /proc/cpuinfo. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Re-write commit message (Thomas) arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cp

[PATCH v6 06/12] x86/msr-index: Define IA32_PASID MSR

2020-07-13 Thread Fenghua Yu
The IA32_PASID MSR (0xd93) contains the Process Address Space Identifier (PASID), a 20-bit value. Bit 31 must be set to indicate the value programmed in the MSR is valid. Hardware uses PASID to identify process address space and direct responses to the right address space. Signed-off-by: Fenghua

[PATCH v6 11/12] sched: Define and initialize a flag to identify valid PASID in the task

2020-07-13 Thread Fenghua Yu
From: Peter Zijlstra The flag is defined for the task to identify if the task has a valid PASID. Its initial value is 0 when the task is forked/cloned. It will be used shortly. Signed-off-by: Peter Zijlstra Co-developed-by: Fenghua Yu Signed-off-by: Fenghua Yu --- v2: - Add this patch

[PATCH v6 12/12] x86/traps: Fix up invalid PASID

2020-07-13 Thread Fenghua Yu
reason 3) Try initializing the PASID MSR and returning. If the #GP was from an ENQCMD this will fix it. If not, the #GP fault will be repeated and will hit case "2". Suggested-by: Thomas Gleixner Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck Reviewed-by: Lu Baolu ---

[PATCH v6 00/12] x86: tag application address space for devices

2020-07-13 Thread Fenghua Yu
t (Christoph). Jean-Philippe Brucker released a virtually same patch. Upstream only needs one of the two. - Add patch 9 to initialize PASID in a new mm. - Plus other changes described in each patch (Thomas) Ashok Raj (1): docs: x86: Add documentation for SVA (Shared Virtual Addressing) Fenghua Y

[PATCH v6 07/12] mm: Define pasid in mm

2020-07-13 Thread Fenghua Yu
PASID is shared by all threads in a process. So the logical place to keep track of it is in the "mm". Both ARM and X86 need to use the PASID in the "mm". Suggested-by: Christoph Hellwig Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v4: - Change PASID type to

Re: [PATCH v6 01/12] iommu: Change type of pasid to u32

2020-07-14 Thread Fenghua Yu
On Mon, Jul 13, 2020 at 07:45:49PM -0700, Liu, Yi L wrote: > > From: Fenghua Yu > > Sent: Tuesday, July 14, 2020 7:48 AM > > > > PASID is defined as a few different types in iommu including "int", > > "u32", and "unsigned int". To be con

[PATCH v5 09/12] x86/process: Clear PASID state for a newly forked/cloned thread

2020-06-30 Thread Fenghua Yu
s Gleixner Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Modify init_task_pasid(). arch/x86/kernel/process.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index f362ce0d5ac0..1b1492e337a6 100644 --- a/arch/

[PATCH v5 03/12] docs: x86: Add documentation for SVA (Shared Virtual Addressing)

2020-06-30 Thread Fenghua Yu
From: Ashok Raj ENQCMD and Data Streaming Accelerator (DSA) and all of their associated features are a complicated stack with lots of interconnected pieces. This documentation provides a big picture overview for all of the features. Signed-off-by: Ashok Raj Co-developed-by: Fenghua Yu Signed

[PATCH v5 01/12] iommu: Change type of pasid to u32

2020-06-30 Thread Fenghua Yu
xplicit than "unsigned int". No PASID type change in uapi although it defines PASID as __u64 in some places. Suggested-by: Thomas Gleixner Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck Reviewed-by: Lu Baolu --- v5: - Reviewed by Lu Baolu v4: - Change PASID type from &quo

[PATCH v5 08/12] fork: Clear PASID for new mm

2020-06-30 Thread Fenghua Yu
When a new mm is created, its PASID should be cleared, i.e. the PASID is initialized to its init state 0 on both ARM and X86. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Add this patch to initialize PASID value for a new mm. include/linux/mm_types.h | 2 ++ kernel/fork.c

[PATCH v5 04/12] x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions

2020-06-30 Thread Fenghua Yu
in ENQCMDS. There isn't any usage of ENQCMD in the kernel as of now. The CPU feature flag is shown as "enqcmd" in /proc/cpuinfo. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Re-write commit message (Thomas) arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cp

[PATCH v5 07/12] mm: Define pasid in mm

2020-06-30 Thread Fenghua Yu
PASID is shared by all threads in a process. So the logical place to keep track of it is in the "mm". Both ARM and X86 need to use the PASID in the "mm". Suggested-by: Christoph Hellwig Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v4: - Change PASID type to

[PATCH v5 02/12] iommu/vt-d: Change flags type to unsigned int in binding mm

2020-06-30 Thread Fenghua Yu
"flags" passed to intel_svm_bind_mm() is a bit mask and should be defined as "unsigned int" instead of "int". Change its type to "unsigned int". Suggested-by: Thomas Gleixner Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck Reviewed-by: Lu Baolu -

[PATCH v5 05/12] x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature

2020-06-30 Thread Fenghua Yu
From: Yu-cheng Yu ENQCMD instruction reads PASID from IA32_PASID MSR. The MSR is stored in the task's supervisor FPU PASID state and is context switched by XSAVES/XRSTORS. Signed-off-by: Yu-cheng Yu Co-developed-by: Fenghua Yu Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2

[PATCH v5 11/12] sched: Define and initialize a flag to identify valid PASID in the task

2020-06-30 Thread Fenghua Yu
From: Peter Zijlstra The flag is defined for the task to identify if the task has a valid PASID. Its initial value is 0 when the task is forked/cloned. It will be used shortly. Signed-off-by: Peter Zijlstra Co-developed-by: Fenghua Yu Signed-off-by: Fenghua Yu --- v2: - Add this patch

[PATCH v5 12/12] x86/traps: Fix up invalid PASID

2020-06-30 Thread Fenghua Yu
reason 3) Try initializing the PASID MSR and returning. If the #GP was from an ENQCMD this will fix it. If not, the #GP fault will be repeated and will hit case "2". Suggested-by: Thomas Gleixner Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck Reviewed-by: Lu Baolu ---

[PATCH v5 06/12] x86/msr-index: Define IA32_PASID MSR

2020-06-30 Thread Fenghua Yu
The IA32_PASID MSR (0xd93) contains the Process Address Space Identifier (PASID), a 20-bit value. Bit 31 must be set to indicate the value programmed in the MSR is valid. Hardware uses PASID to identify process address space and direct responses to the right address space. Signed-off-by: Fenghua

[PATCH v5 10/12] x86/mmu: Allocate/free PASID

2020-06-30 Thread Fenghua Yu
w many SVM devices are sharing the PASID). Currently the ENQCMD feature cannot be used if CONFIG_INTEL_IOMMU_SVM is not set. Add X86_FEATURE_ENQCMD to the disabled features mask as appropriate and use cpu_feature_enabled() to check the feature. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck Revie

[PATCH v5 00/12] x86: tag application address space for devices

2020-06-30 Thread Fenghua Yu
" to generic mm_struct (Christoph). Jean-Philippe Brucker released a virtually same patch. Upstream only needs one of the two. - Add patch 9 to initialize PASID in a new mm. - Plus other changes described in each patch (Thomas) Ashok Raj (1): docs: x86: Add documentation for SVA (Share

Re: [PATCH v2 12/12] x86/traps: Fix up invalid PASID

2020-06-15 Thread Fenghua Yu
Hi, Peter, On Mon, Jun 15, 2020 at 08:31:16PM +0200, Peter Zijlstra wrote: > On Mon, Jun 15, 2020 at 11:12:59AM -0700, Fenghua Yu wrote: > > > I don't get why you need a rdmsr here, or why not having one would > > > require a TIF flag. Is that because this MSR is XSAVE/XRSTOR

Re: [PATCH v2 12/12] x86/traps: Fix up invalid PASID

2020-06-15 Thread Fenghua Yu
Hi, Peter, On Mon, Jun 15, 2020 at 09:09:28PM +0200, Peter Zijlstra wrote: > On Mon, Jun 15, 2020 at 11:55:29AM -0700, Fenghua Yu wrote: > > > Or do you suggest to add a random new flag in struct thread_info instead > > of a TIF flag? > > Why thread_info? What's wrong wi

Re: [PATCH v2 12/12] x86/traps: Fix up invalid PASID

2020-06-15 Thread Fenghua Yu
On Mon, Jun 15, 2020 at 06:03:57PM +0200, Peter Zijlstra wrote: > On Mon, Jun 15, 2020 at 08:48:54AM -0700, Fenghua Yu wrote: > > Hi, Peter, > > On Mon, Jun 15, 2020 at 09:56:49AM +0200, Peter Zijlstra wrote: > > > On Fri, Jun 12, 2020 at 05:41:33PM

[PATCH v3 06/13] x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature

2020-06-17 Thread Fenghua Yu
From: Yu-cheng Yu ENQCMD instruction reads PASID from IA32_PASID MSR. The MSR is stored in the task's supervisor FPU PASID state and is context switched by XSAVES/XRSTORS. Signed-off-by: Yu-cheng Yu Co-developed-by: Fenghua Yu Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2

[PATCH v3 09/13] fork: Clear PASID for new mm

2020-06-17 Thread Fenghua Yu
When a new mm is created, its PASID should be cleared, i.e. the PASID is initialized to its init state 0 on both ARM and X86. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Add this patch to initialize PASID value for a new mm. include/linux/mm_types.h | 2 ++ kernel/fork.c

[PATCH v3 12/13] sched: Define and initialize a flag to identify valid PASID in the task

2020-06-17 Thread Fenghua Yu
From: Peter Zijlstra The flag is defined for the task to identify if the task has a valid PASID. Its initial value is 0 when the task is forked/cloned. It will be used shortly. Signed-off-by: Peter Zijlstra Co-developed-by: Fenghua Yu Signed-off-by: Fenghua Yu --- v2: - Add this patch

[PATCH v3 07/13] x86/msr-index: Define IA32_PASID MSR

2020-06-17 Thread Fenghua Yu
The IA32_PASID MSR (0xd93) contains the Process Address Space Identifier (PASID), a 20-bit value. Bit 31 must be set to indicate the value programmed in the MSR is valid. Hardware uses PASID to identify process address space and direct responses to the right address space. Signed-off-by: Fenghua

[PATCH v3 11/13] x86/mmu: Allocate/free PASID

2020-06-17 Thread Fenghua Yu
w many SVM devices are sharing the PASID). Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v3: - Add sanity checks in alloc_pasid() and _free_pasid() (Baolu) - Add a comment that the private PASID feature will be removed completely from IOMMU and don't track private PASID in mm (Thomas) v2

[PATCH v3 01/13] iommu: Change type of pasid to unsigned int

2020-06-17 Thread Fenghua Yu
PASID is defined as a few different types in iommu including "int", "u32", and "unsigned int". To be consistent and to match with ioasid's type, define PASID and its variations (e.g. max PASID) as "unsigned int". No PASID type change in uapi. Suggested-by:

[PATCH v3 05/13] x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions

2020-06-17 Thread Fenghua Yu
in ENQCMDS. There isn't any usage of ENQCMD in the kernel as of now. The CPU feature flag is shown as "enqcmd" in /proc/cpuinfo. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Re-write commit message (Thomas) arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cp

[PATCH v3 08/13] mm: Define pasid in mm

2020-06-17 Thread Fenghua Yu
PASID is shared by all threads in a process. So the logical place to keep track of it is in the "mm". Both ARM and X86 need to use the PASID in the "mm". Suggested-by: Christoph Hellwig Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v3: - Change CONFIG_PCI_PASID to

[PATCH v3 04/13] docs: x86: Add documentation for SVA (Shared Virtual Addressing)

2020-06-17 Thread Fenghua Yu
From: Ashok Raj ENQCMD and Data Streaming Accelerator (DSA) and all of their associated features are a complicated stack with lots of interconnected pieces. This documentation provides a big picture overview for all of the features. Signed-off-by: Ashok Raj Co-developed-by: Fenghua Yu Signed

[PATCH v3 02/13] ocxl: Change type of pasid to unsigned int

2020-06-17 Thread Fenghua Yu
PASID is defined as "int" although it's a 20-bit value and shouldn't be negative int. To be consistent with type defined in iommu, define PASID as "unsigned int". Suggested-by: Thomas Gleixner Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Create this new p

[PATCH v3 03/13] iommu/vt-d: Change flags type to unsigned int in binding mm

2020-06-17 Thread Fenghua Yu
"flags" passed to intel_svm_bind_mm() is a bit mask and should be defined as "unsigned int" instead of "int". Change its type to "unsigned int". Suggested-by: Thomas Gleixner Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Add this new pa

[PATCH v3 00/13] x86: tag application address space for devices

2020-06-17 Thread Fenghua Yu
_struct (Christoph). Jean-Philippe Brucker released a virtually same patch. Upstream only needs one of the two. - Add patch 9 to initialize PASID in a new mm. - Plus other changes described in each patch (Thomas) Ashok Raj (1): docs: x86: Add documentation for SVA (Shared Virtual Addressing) Feng

[PATCH v3 10/13] x86/process: Clear PASID state for a newly forked/cloned thread

2020-06-17 Thread Fenghua Yu
s Gleixner Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Modify init_task_pasid(). arch/x86/kernel/process.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index f362ce0d5ac0..1b1492e337a6 100644 --- a/arch/

[PATCH v3 13/13] x86/traps: Fix up invalid PASID

2020-06-17 Thread Fenghua Yu
reason 3) Try initializing the PASID MSR and returning. If the #GP was from an ENQCMD this will fix it. If not, the #GP fault will be repeated and will hit case "2". Suggested-by: Thomas Gleixner Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v3: - Check and s

Re: [PATCH v3 01/13] iommu: Change type of pasid to unsigned int

2020-06-18 Thread Fenghua Yu
On Thu, Jun 18, 2020 at 12:12:06AM -0700, Christoph Hellwig wrote: > On Wed, Jun 17, 2020 at 11:23:41AM -0700, Fenghua Yu wrote: > > PASID is defined as a few different types in iommu including "int", > > "u32", and "unsigned int". To be consistent and

Re: [PATCH v2 02/12] ocxl: Change type of pasid to unsigned int

2020-06-18 Thread Fenghua Yu
Hi, Frederic, On Thu, Jun 18, 2020 at 10:05:19AM +0200, Frederic Barrat wrote: > > > Le 13/06/2020 à 02:41, Fenghua Yu a écrit : > >PASID is defined as "int" although it's a 20-bit value and shouldn't be > >negative int. To be consistent with type defined in iomm

Re: [PATCH v3 01/13] iommu: Change type of pasid to unsigned int

2020-06-22 Thread Fenghua Yu
Hi, Christoph, On Thu, Jun 18, 2020 at 12:12:06AM -0700, Christoph Hellwig wrote: > On Wed, Jun 17, 2020 at 11:23:41AM -0700, Fenghua Yu wrote: > > PASID is defined as a few different types in iommu including "int", > > "u32", and "unsigned int"

[PATCH v4 06/12] x86/msr-index: Define IA32_PASID MSR

2020-06-25 Thread Fenghua Yu
The IA32_PASID MSR (0xd93) contains the Process Address Space Identifier (PASID), a 20-bit value. Bit 31 must be set to indicate the value programmed in the MSR is valid. Hardware uses PASID to identify process address space and direct responses to the right address space. Signed-off-by: Fenghua

[PATCH v4 01/12] iommu: Change type of pasid to u32

2020-06-25 Thread Fenghua Yu
xplicit than "unsigned int". No PASID type change in uapi although it defines PASID as __u64 in some places. Suggested-by: Thomas Gleixner Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v4: - Change PASID type from "unsigned int" to "u32" (Christoph) v2: -

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