From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch implements workaround for the AMD Family15h Model10-1Fh erratum 746.
(http://support.amd.com/us/Processor_TechDocs/48931_15h_Mod_10h-1Fh_Rev_Guide.pdf)
Signed-off-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
diff
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Changes in V3:
* Add proper commit message
* Change logic to avoid unnecessary indentaion
Changes in V2:
* Fix logic that check the processor model.
* Clear write enable bit after apply workaround
*
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
The IOMMU may stop processing page translations due to a perceived lack
of credits for writing upstream peripheral page service request (PPR)
or event logs. If the L2B miscellaneous clock gating feature is enabled
the IOMMU does not
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Add logic to decode AMD IOMMU event flag based on information from AMD IOMMU
specification.
This should simplify debugging IOMMU errors. Also, dump DTE information in
additional cases.
Signed-off-by: Suravee Suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Add logic to decode AMD IOMMU event flag based on information from AMD IOMMU
specification.
This should simplify debugging IOMMU errors. Also, dump DTE information in
additional cases.
Signed-off-by: Suravee Suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Add logic to decode AMD IOMMU event flag based on information from AMD IOMMU
specification.
This should simplify debugging IOMMU errors. Also, dump DTE information in
additional cases.
This is an example:
AMD-Vi: Event logged
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
The IOMMU interrupt handling in bottom half must clear the PPR log interrupt
and event log interrupt bits to re-enable the interrupt. This is done by
writing 1 to the memory mapped register to clear the bit. Due to hardware bug,
if the
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Add logic to decode AMD IOMMU event flag based on information from AMD IOMMU
specification.
This should simplify debugging IOMMU errors. Also, dump DTE information in
additional cases.
This is an example:
AMD-Vi: Event logged
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch set add detail event log information for AMD IOMMU in dmesg when
booting with
amd-iommu=verbose.
Suravee Suthikulpanit (2):
iommu/amd: Adding new command line option amd-iommu=verbose
iommu/amd: Add logic to decode AMD
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Adding new command line option amd-iommu=verbose to allow verbose print out
in dmesg.
Signed-off-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
---
drivers/iommu/amd_iommu_init.c |4
drivers/iommu/amd_iommu_types.h |
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
The IOMMU interrupt handling in bottom half must clear the PPR log interrupt
and event log interrupt bits to re-enable the interrupt. This is done by
writing 1 to the memory mapped register to clear the bit. Due to hardware bug,
if the
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
In the current interrupt handling scheme, there are as many threads as
the number of IOMMUs. Each thread is created and assigned to an IOMMU at
the time of registering interrupt handlers (request_threaded_irq).
When an IOMMU HW generates
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
In the current interrupt handling scheme, there are as many threads as
the number of IOMMUs. Each thread is created and assigned to an IOMMU at
the time of registering interrupt handlers (request_threaded_irq).
When an IOMMU HW generates
From: Steven L Kinney steven.kin...@amd.com
Add functionality to check the availability of the AMD IOMMU Performance
Counters and export this functionality to other core drivers, such as in this
case, a perf AMD IOMMU PMU. This feature is not bound to any specific AMD
family/model other than the
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
These patches implement the AMD IOMMU Performance Counter functionality
via custom perf PMU and implement static counting for various IOMMU
translations.
1) Extend the AMD IOMMU initialization to include performance
counter
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Adding amd_iommu_log command line option to allow default, verbose and
debug
IOMMU error logging level in kernel log.
Signed-off-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
---
Documentation/kernel-parameters.txt | 10
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Remove old event printing logic and hook up with the new event
handling logic in amd_iommu_fault.c
Signed-off-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
---
drivers/iommu/amd_iommu.c | 85
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch set implements framework for handling errors reported via IOMMU
event log. It also implements mechanism to filter/suppress error messages when
IOMMU hardware generates large amount event logs, which is often caused by
devices
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Implement a perf PMU to handle IOMMU performance counters and events.
The PMU only supports counting mode (e.g. perf stat). Since the counters
are shared across all cores, the PMU is implemented as system-wide mode.
To invoke the AMD
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
These patches implement the AMD IOMMU Performance Counter functionality
via custom perf PMU and implement static counting for various IOMMU
translations.
1) Extend the AMD IOMMU initialization to include performance
counter
From: Steven L Kinney steven.kin...@amd.com
Add functionality to check the availability of the AMD IOMMU Performance
Counters and export this functionality to other core drivers, such as in this
case, a perf AMD IOMMU PMU. This feature is not bound to any specific AMD
family/model other than the
From: Jay Cornwall jay.cornw...@amd.com
This patch corrects the PASID format in the INVALIDATE_IOTLB_PAGES
command, which was caused by incorrect information in
the AMD IOMMU Architectural Specification v2.01 document.
Incorrect format:
cmd-data[0][16:23] = PASID[7:0]
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
In reality, the spec can only support 16-bit PASID since
INVALIDATE_IOTLB_PAGES and COMPLETE_PPR_REQUEST commands only allow 16-bit
PASID. So, we updated the PASID_MASK accordingly and invoke BUG_ON
if the hardware is reporting PASmax more
From: Jay Cornwall jay.cornw...@amd.com
get_user_pages requires caller to hold a read lock on mmap_sem.
Signed-off-by: Jay Cornwall jay.cornw...@amd.com
Signed-off-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
---
drivers/iommu/amd_iommu_v2.c |2 ++
1 file changed, 2 insertions(+)
From: Jay Cornwall jay.cornw...@amd.com
Do not disassociate the process page tables from a PASID during VM
invalidation. Invalidate the IOMMU TLB and IOTLBs before invalidation.
L2 translations may fail during VM range invalidation. The current
implementation associates an empty page table with
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