Re: [PATCH v1 16/16] arm64: dts: mt8195: Add display node for vdosys0
On Mon, 2022-07-04 at 14:39 +0200, Krzysztof Kozlowski wrote:
> On 04/07/2022 12:00, Tinghan Shen wrote:
> > From: "Jason-JH.Lin"
> >
> > Add display node for vdosys0 of mt8195.
> >
> > Signed-off-by: Jason-JH.Lin
> > Signed-off-by: Tinghan Shen
> > ---
> > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 109 +++
> > 1 file changed, 109 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > index 724c6ca837b6..faea8ef33e5a 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > @@ -1961,6 +1961,7 @@
> > vdosys0: syscon@1c01a000 {
> > compatible = "mediatek,mt8195-mmsys", "syscon";
> > reg = <0 0x1c01a000 0 0x1000>;
> > + mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
> > #clock-cells = <1>;
> > };
> >
> > @@ -1976,6 +1977,114 @@
> > power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
> > };
> >
> > + ovl0: ovl@1c00 {
> > + compatible = "mediatek,mt8195-disp-ovl",
> > +"mediatek,mt8183-disp-ovl";
> > + reg = <0 0x1c00 0 0x1000>;
> > + interrupts = ;
> > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> > + clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
> > + iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
> > + mediatek,gce-client-reg =
> > +<&gce0 SUBSYS_1c00 0x 0x1000>;
> > + };
> > +
> > + rdma0: rdma@1c002000 {
> > + compatible = "mediatek,mt8195-disp-rdma";
> > + reg = <0 0x1c002000 0 0x1000>;
> > + interrupts = ;
> > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> > + clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
> > + iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
> > + mediatek,gce-client-reg =
> > +<&gce0 SUBSYS_1c00 0x2000 0x1000>;
> > + };
> > +
> > + color0: color@1c003000 {
> > + compatible = "mediatek,mt8195-disp-color",
> > +"mediatek,mt8173-disp-color";
> > + reg = <0 0x1c003000 0 0x1000>;
> > + interrupts = ;
> > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> > + clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
> > + mediatek,gce-client-reg =
> > +<&gce0 SUBSYS_1c00 0x3000 0x1000>;
> > + };
> > +
> > + ccorr0: ccorr@1c004000 {
> > + compatible = "mediatek,mt8195-disp-ccorr",
> > +"mediatek,mt8192-disp-ccorr";
> > + reg = <0 0x1c004000 0 0x1000>;
> > + interrupts = ;
> > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> > + clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
> > + mediatek,gce-client-reg =
> > +<&gce0 SUBSYS_1c00 0x4000 0x1000>;
> > + };
> > +
> > + aal0: aal@1c005000 {
> > + compatible = "mediatek,mt8195-disp-aal",
> > +"mediatek,mt8183-disp-aal";
> > + reg = <0 0x1c005000 0 0x1000>;
> > + interrupts = ;
> > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> > + clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
> > + mediatek,gce-client-reg =
> > +<&gce0 SUBSYS_1c00 0x5000 0x1000>;
> > + };
> > +
> > + gamma0: gamma@1c006000 {
> > + compatible = "mediatek,mt8195-disp-gamma",
> > +"mediatek,mt8183-disp-gamma";
> > + reg = <0 0x1c006000 0 0x1000>;
> > + interrupts = ;
> > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> > + clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
> > + mediatek,gce-client-reg =
> > +<&gce0 SUBSYS_1c00 0x6000 0x1000>;
> > + };
> > +
> > + dither0: dither@1c007000 {
> > + compatible = "mediatek,mt8195-disp-dither",
> > +"mediatek,mt8183-disp-dither";
> > + reg = <0 0x1c007000 0 0x1000>;
> > + interrupts = ;
> > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> > + clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
> > + mediatek,gce-client-reg =
> > +<&gce0 SUB
Re: [PATCH v1 16/16] arm64: dts: mt8195: Add display node for vdosys0
On Mon, 2022-07-04 at 12:44 +0200, AngeloGioacchino Del Regno wrote:
> Il 04/07/22 12:00, Tinghan Shen ha scritto:
> > From: "Jason-JH.Lin"
> >
> > Add display node for vdosys0 of mt8195.
> >
> > Signed-off-by: Jason-JH.Lin
> > Signed-off-by: Tinghan Shen
> > ---
> > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 109 +++
> > 1 file changed, 109 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > index 724c6ca837b6..faea8ef33e5a 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > @@ -1961,6 +1961,7 @@
> > vdosys0: syscon@1c01a000 {
> > compatible = "mediatek,mt8195-mmsys", "syscon";
> > reg = <0 0x1c01a000 0 0x1000>;
> > + mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
> > #clock-cells = <1>;
> > };
> >
> > @@ -1976,6 +1977,114 @@
> > power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
> > };
> >
> > + ovl0: ovl@1c00 {
> > + compatible = "mediatek,mt8195-disp-ovl",
> > +"mediatek,mt8183-disp-ovl";
>
> This fits in one line, please fix, here and all of the other instances of
> that.
>
> > + reg = <0 0x1c00 0 0x1000>;
> > + interrupts = ;
> > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> > + clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
> > + iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
> > + mediatek,gce-client-reg =
> > +<&gce0 SUBSYS_1c00 0x 0x1000>;
>
> Same for gce-client-reg.
>
> Regards,
> Angelo
Ok, I'll update in next version.
Thanks,
TingHan
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Re: [PATCH v1 16/16] arm64: dts: mt8195: Add display node for vdosys0
On 04/07/2022 12:00, Tinghan Shen wrote:
> From: "Jason-JH.Lin"
>
> Add display node for vdosys0 of mt8195.
>
> Signed-off-by: Jason-JH.Lin
> Signed-off-by: Tinghan Shen
> ---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 109 +++
> 1 file changed, 109 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 724c6ca837b6..faea8ef33e5a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -1961,6 +1961,7 @@
> vdosys0: syscon@1c01a000 {
> compatible = "mediatek,mt8195-mmsys", "syscon";
> reg = <0 0x1c01a000 0 0x1000>;
> + mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
> #clock-cells = <1>;
> };
>
> @@ -1976,6 +1977,114 @@
> power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
> };
>
> + ovl0: ovl@1c00 {
> + compatible = "mediatek,mt8195-disp-ovl",
> + "mediatek,mt8183-disp-ovl";
> + reg = <0 0x1c00 0 0x1000>;
> + interrupts = ;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> + clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
> + iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
> + mediatek,gce-client-reg =
> + <&gce0 SUBSYS_1c00 0x 0x1000>;
> + };
> +
> + rdma0: rdma@1c002000 {
> + compatible = "mediatek,mt8195-disp-rdma";
> + reg = <0 0x1c002000 0 0x1000>;
> + interrupts = ;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> + clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
> + iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
> + mediatek,gce-client-reg =
> + <&gce0 SUBSYS_1c00 0x2000 0x1000>;
> + };
> +
> + color0: color@1c003000 {
> + compatible = "mediatek,mt8195-disp-color",
> + "mediatek,mt8173-disp-color";
> + reg = <0 0x1c003000 0 0x1000>;
> + interrupts = ;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> + clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
> + mediatek,gce-client-reg =
> + <&gce0 SUBSYS_1c00 0x3000 0x1000>;
> + };
> +
> + ccorr0: ccorr@1c004000 {
> + compatible = "mediatek,mt8195-disp-ccorr",
> + "mediatek,mt8192-disp-ccorr";
> + reg = <0 0x1c004000 0 0x1000>;
> + interrupts = ;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> + clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
> + mediatek,gce-client-reg =
> + <&gce0 SUBSYS_1c00 0x4000 0x1000>;
> + };
> +
> + aal0: aal@1c005000 {
> + compatible = "mediatek,mt8195-disp-aal",
> + "mediatek,mt8183-disp-aal";
> + reg = <0 0x1c005000 0 0x1000>;
> + interrupts = ;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> + clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
> + mediatek,gce-client-reg =
> + <&gce0 SUBSYS_1c00 0x5000 0x1000>;
> + };
> +
> + gamma0: gamma@1c006000 {
> + compatible = "mediatek,mt8195-disp-gamma",
> + "mediatek,mt8183-disp-gamma";
> + reg = <0 0x1c006000 0 0x1000>;
> + interrupts = ;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> + clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
> + mediatek,gce-client-reg =
> + <&gce0 SUBSYS_1c00 0x6000 0x1000>;
> + };
> +
> + dither0: dither@1c007000 {
> + compatible = "mediatek,mt8195-disp-dither",
> + "mediatek,mt8183-disp-dither";
> + reg = <0 0x1c007000 0 0x1000>;
> + interrupts = ;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> + clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
> + mediatek,gce-client-reg =
> + <&gce0 SUBSYS_1c00 0x7000 0x1000>;
> + };
> +
> + dsc0: dsc@1c009000 {
> + c
[PATCH v1 16/16] arm64: dts: mt8195: Add display node for vdosys0
From: "Jason-JH.Lin"
Add display node for vdosys0 of mt8195.
Signed-off-by: Jason-JH.Lin
Signed-off-by: Tinghan Shen
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 109 +++
1 file changed, 109 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 724c6ca837b6..faea8ef33e5a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1961,6 +1961,7 @@
vdosys0: syscon@1c01a000 {
compatible = "mediatek,mt8195-mmsys", "syscon";
reg = <0 0x1c01a000 0 0x1000>;
+ mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
#clock-cells = <1>;
};
@@ -1976,6 +1977,114 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
};
+ ovl0: ovl@1c00 {
+ compatible = "mediatek,mt8195-disp-ovl",
+"mediatek,mt8183-disp-ovl";
+ reg = <0 0x1c00 0 0x1000>;
+ interrupts = ;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
+ iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
+ mediatek,gce-client-reg =
+<&gce0 SUBSYS_1c00 0x 0x1000>;
+ };
+
+ rdma0: rdma@1c002000 {
+ compatible = "mediatek,mt8195-disp-rdma";
+ reg = <0 0x1c002000 0 0x1000>;
+ interrupts = ;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
+ iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+ mediatek,gce-client-reg =
+<&gce0 SUBSYS_1c00 0x2000 0x1000>;
+ };
+
+ color0: color@1c003000 {
+ compatible = "mediatek,mt8195-disp-color",
+"mediatek,mt8173-disp-color";
+ reg = <0 0x1c003000 0 0x1000>;
+ interrupts = ;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
+ mediatek,gce-client-reg =
+<&gce0 SUBSYS_1c00 0x3000 0x1000>;
+ };
+
+ ccorr0: ccorr@1c004000 {
+ compatible = "mediatek,mt8195-disp-ccorr",
+"mediatek,mt8192-disp-ccorr";
+ reg = <0 0x1c004000 0 0x1000>;
+ interrupts = ;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
+ mediatek,gce-client-reg =
+<&gce0 SUBSYS_1c00 0x4000 0x1000>;
+ };
+
+ aal0: aal@1c005000 {
+ compatible = "mediatek,mt8195-disp-aal",
+"mediatek,mt8183-disp-aal";
+ reg = <0 0x1c005000 0 0x1000>;
+ interrupts = ;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
+ mediatek,gce-client-reg =
+<&gce0 SUBSYS_1c00 0x5000 0x1000>;
+ };
+
+ gamma0: gamma@1c006000 {
+ compatible = "mediatek,mt8195-disp-gamma",
+"mediatek,mt8183-disp-gamma";
+ reg = <0 0x1c006000 0 0x1000>;
+ interrupts = ;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
+ mediatek,gce-client-reg =
+<&gce0 SUBSYS_1c00 0x6000 0x1000>;
+ };
+
+ dither0: dither@1c007000 {
+ compatible = "mediatek,mt8195-disp-dither",
+"mediatek,mt8183-disp-dither";
+ reg = <0 0x1c007000 0 0x1000>;
+ interrupts = ;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
+ mediatek,gce-client-reg =
+<&gce0 SUBSYS_1c00 0x7000 0x1000>;
+ };
+
+ dsc0: dsc@1c009000 {
+ compatible = "mediatek,mt8195-disp-dsc";
+ reg = <0 0x1c009000 0 0x1000>
Re: [PATCH v1 16/16] arm64: dts: mt8195: Add display node for vdosys0
Il 04/07/22 12:00, Tinghan Shen ha scritto:
From: "Jason-JH.Lin"
Add display node for vdosys0 of mt8195.
Signed-off-by: Jason-JH.Lin
Signed-off-by: Tinghan Shen
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 109 +++
1 file changed, 109 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 724c6ca837b6..faea8ef33e5a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1961,6 +1961,7 @@
vdosys0: syscon@1c01a000 {
compatible = "mediatek,mt8195-mmsys", "syscon";
reg = <0 0x1c01a000 0 0x1000>;
+ mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
#clock-cells = <1>;
};
@@ -1976,6 +1977,114 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
};
+ ovl0: ovl@1c00 {
+ compatible = "mediatek,mt8195-disp-ovl",
+"mediatek,mt8183-disp-ovl";
This fits in one line, please fix, here and all of the other instances of that.
+ reg = <0 0x1c00 0 0x1000>;
+ interrupts = ;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
+ iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
+ mediatek,gce-client-reg =
+<&gce0 SUBSYS_1c00 0x 0x1000>;
Same for gce-client-reg.
Regards,
Angelo
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