Re: [PATCH v3 2/7] iommu/vt-d: Remove global page support in devTLB flush
On Thu, 2 Jul 2020 09:16:22 +0200 Auger Eric wrote: > Hi Jacob, > > On 7/1/20 5:33 PM, Jacob Pan wrote: > > Global pages support is removed from VT-d spec 3.0 for dev TLB > > invalidation. This patch is to remove the bits for vSVA. Similar > > change already made for the native SVA. See the link below. > > > > Link: https://lkml.org/lkml/2019/8/26/651 > > Acked-by: Lu Baolu > > Signed-off-by: Jacob Pan > > --- > > drivers/iommu/intel/dmar.c | 4 +--- > > drivers/iommu/intel/iommu.c | 4 ++-- > > include/linux/intel-iommu.h | 3 +-- > > 3 files changed, 4 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c > > index cc46dff98fa0..d9f973fa1190 100644 > > --- a/drivers/iommu/intel/dmar.c > > +++ b/drivers/iommu/intel/dmar.c > > @@ -1437,8 +1437,7 @@ void qi_flush_piotlb(struct intel_iommu > > *iommu, u16 did, u32 pasid, u64 addr, > > /* PASID-based device IOTLB Invalidate */ > > void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, > > u16 pfsid, > > - u32 pasid, u16 qdep, u64 addr, > > - unsigned int size_order, u64 granu) > > + u32 pasid, u16 qdep, u64 addr, > > unsigned int size_order) { > > unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - > > 1); struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0}; > > @@ -1446,7 +1445,6 @@ void qi_flush_dev_iotlb_pasid(struct > > intel_iommu *iommu, u16 sid, u16 pfsid, desc.qw0 = > > QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) | > > QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE | > > QI_DEV_IOTLB_PFSID(pfsid); > > - desc.qw1 = QI_DEV_EIOTLB_GLOB(granu); > nit: > > you may simplify the init of .qw1 to > .qw1 = addr & ~mask > > as you have > desc.qw1 |= addr & ~mask; > indeed, will change it in patch 4/7. Thanks! > Besides > Reviewed-by: Eric Auger > > Thanks > > Eric > > > > > /* > > * If S bit is 0, we only flush a single page. If S bit is > > set, diff --git a/drivers/iommu/intel/iommu.c > > b/drivers/iommu/intel/iommu.c index 9129663a7406..96340da57075 > > 100644 --- a/drivers/iommu/intel/iommu.c > > +++ b/drivers/iommu/intel/iommu.c > > @@ -5466,7 +5466,7 @@ intel_iommu_sva_invalidate(struct > > iommu_domain *domain, struct device *dev, info->pfsid, pasid, > > info->ats_qdep, > > inv_info->addr_info.addr, > > - size, granu); > > + size); > > break; > > case IOMMU_CACHE_INV_TYPE_DEV_IOTLB: > > if (info->ats_enabled) > > @@ -5474,7 +5474,7 @@ intel_iommu_sva_invalidate(struct > > iommu_domain *domain, struct device *dev, info->pfsid, pasid, > > info->ats_qdep, > > inv_info->addr_info.addr, > > - size, granu); > > + size); > > else > > pr_warn_ratelimited("Passdown > > device IOTLB flush w/o ATS!\n"); break; > > diff --git a/include/linux/intel-iommu.h > > b/include/linux/intel-iommu.h index 729386ca8122..9a6614880773 > > 100644 --- a/include/linux/intel-iommu.h > > +++ b/include/linux/intel-iommu.h > > @@ -380,7 +380,6 @@ enum { > > > > #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK) > > #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11) > > -#define QI_DEV_EIOTLB_GLOB(g) ((u64)(g) & 0x1) > > #define QI_DEV_EIOTLB_PASID(p) ((u64)((p) & 0xf) << 32) > > #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0x) << 16) > > #define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4) > > @@ -704,7 +703,7 @@ void qi_flush_piotlb(struct intel_iommu *iommu, > > u16 did, u32 pasid, u64 addr, > > void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, > > u16 pfsid, u32 pasid, u16 qdep, u64 addr, > > - unsigned int size_order, u64 granu); > > + unsigned int size_order); > > void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 > > granu, int pasid); > > > > > [Jacob Pan] ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH v3 2/7] iommu/vt-d: Remove global page support in devTLB flush
Hi Jacob, On 7/1/20 5:33 PM, Jacob Pan wrote: > Global pages support is removed from VT-d spec 3.0 for dev TLB > invalidation. This patch is to remove the bits for vSVA. Similar change > already made for the native SVA. See the link below. > > Link: https://lkml.org/lkml/2019/8/26/651 > Acked-by: Lu Baolu > Signed-off-by: Jacob Pan > --- > drivers/iommu/intel/dmar.c | 4 +--- > drivers/iommu/intel/iommu.c | 4 ++-- > include/linux/intel-iommu.h | 3 +-- > 3 files changed, 4 insertions(+), 7 deletions(-) > > diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c > index cc46dff98fa0..d9f973fa1190 100644 > --- a/drivers/iommu/intel/dmar.c > +++ b/drivers/iommu/intel/dmar.c > @@ -1437,8 +1437,7 @@ void qi_flush_piotlb(struct intel_iommu *iommu, u16 > did, u32 pasid, u64 addr, > > /* PASID-based device IOTLB Invalidate */ > void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, > - u32 pasid, u16 qdep, u64 addr, > - unsigned int size_order, u64 granu) > + u32 pasid, u16 qdep, u64 addr, unsigned int > size_order) > { > unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1); > struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0}; > @@ -1446,7 +1445,6 @@ void qi_flush_dev_iotlb_pasid(struct intel_iommu > *iommu, u16 sid, u16 pfsid, > desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) | > QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE | > QI_DEV_IOTLB_PFSID(pfsid); > - desc.qw1 = QI_DEV_EIOTLB_GLOB(granu); nit: you may simplify the init of .qw1 to .qw1 = addr & ~mask as you have desc.qw1 |= addr & ~mask; Besides Reviewed-by: Eric Auger Thanks Eric > > /* >* If S bit is 0, we only flush a single page. If S bit is set, > diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c > index 9129663a7406..96340da57075 100644 > --- a/drivers/iommu/intel/iommu.c > +++ b/drivers/iommu/intel/iommu.c > @@ -5466,7 +5466,7 @@ intel_iommu_sva_invalidate(struct iommu_domain *domain, > struct device *dev, > info->pfsid, pasid, > info->ats_qdep, > inv_info->addr_info.addr, > - size, granu); > + size); > break; > case IOMMU_CACHE_INV_TYPE_DEV_IOTLB: > if (info->ats_enabled) > @@ -5474,7 +5474,7 @@ intel_iommu_sva_invalidate(struct iommu_domain *domain, > struct device *dev, > info->pfsid, pasid, > info->ats_qdep, > inv_info->addr_info.addr, > - size, granu); > + size); > else > pr_warn_ratelimited("Passdown device IOTLB > flush w/o ATS!\n"); > break; > diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h > index 729386ca8122..9a6614880773 100644 > --- a/include/linux/intel-iommu.h > +++ b/include/linux/intel-iommu.h > @@ -380,7 +380,6 @@ enum { > > #define QI_DEV_EIOTLB_ADDR(a)((u64)(a) & VTD_PAGE_MASK) > #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11) > -#define QI_DEV_EIOTLB_GLOB(g)((u64)(g) & 0x1) > #define QI_DEV_EIOTLB_PASID(p) ((u64)((p) & 0xf) << 32) > #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0x) << 16) > #define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4) > @@ -704,7 +703,7 @@ void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, > u32 pasid, u64 addr, > > void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, > u32 pasid, u16 qdep, u64 addr, > - unsigned int size_order, u64 granu); > + unsigned int size_order); > void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu, > int pasid); > > ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
[PATCH v3 2/7] iommu/vt-d: Remove global page support in devTLB flush
Global pages support is removed from VT-d spec 3.0 for dev TLB invalidation. This patch is to remove the bits for vSVA. Similar change already made for the native SVA. See the link below. Link: https://lkml.org/lkml/2019/8/26/651 Acked-by: Lu Baolu Signed-off-by: Jacob Pan --- drivers/iommu/intel/dmar.c | 4 +--- drivers/iommu/intel/iommu.c | 4 ++-- include/linux/intel-iommu.h | 3 +-- 3 files changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c index cc46dff98fa0..d9f973fa1190 100644 --- a/drivers/iommu/intel/dmar.c +++ b/drivers/iommu/intel/dmar.c @@ -1437,8 +1437,7 @@ void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr, /* PASID-based device IOTLB Invalidate */ void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, - u32 pasid, u16 qdep, u64 addr, - unsigned int size_order, u64 granu) + u32 pasid, u16 qdep, u64 addr, unsigned int size_order) { unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1); struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0}; @@ -1446,7 +1445,6 @@ void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) | QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE | QI_DEV_IOTLB_PFSID(pfsid); - desc.qw1 = QI_DEV_EIOTLB_GLOB(granu); /* * If S bit is 0, we only flush a single page. If S bit is set, diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 9129663a7406..96340da57075 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -5466,7 +5466,7 @@ intel_iommu_sva_invalidate(struct iommu_domain *domain, struct device *dev, info->pfsid, pasid, info->ats_qdep, inv_info->addr_info.addr, - size, granu); + size); break; case IOMMU_CACHE_INV_TYPE_DEV_IOTLB: if (info->ats_enabled) @@ -5474,7 +5474,7 @@ intel_iommu_sva_invalidate(struct iommu_domain *domain, struct device *dev, info->pfsid, pasid, info->ats_qdep, inv_info->addr_info.addr, - size, granu); + size); else pr_warn_ratelimited("Passdown device IOTLB flush w/o ATS!\n"); break; diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h index 729386ca8122..9a6614880773 100644 --- a/include/linux/intel-iommu.h +++ b/include/linux/intel-iommu.h @@ -380,7 +380,6 @@ enum { #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK) #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11) -#define QI_DEV_EIOTLB_GLOB(g) ((u64)(g) & 0x1) #define QI_DEV_EIOTLB_PASID(p) ((u64)((p) & 0xf) << 32) #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0x) << 16) #define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4) @@ -704,7 +703,7 @@ void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr, void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, u32 pasid, u16 qdep, u64 addr, - unsigned int size_order, u64 granu); + unsigned int size_order); void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu, int pasid); -- 2.7.4 ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu