On 13.01.20 10:29, Thorsten Schulz wrote:
Hej group,
I am stuck getting the e1000-demo working in qemu based on
jailhouse-images/wip/update. Due to a prior glitch, I am still on
PREEMPT-RT (./build-image.sh --rt --latest) if that makes a difference.
Upfront maybe as a "bug-note" /if/
From: Nikhil Devshatwar
Add support for Texas Instrument's Peripheral Virtualization Unit
* Define a new IOMMU type and extra fields in the platform_data
* Add new cofig option CONFIG_IOMMU_TI_PVU
* Integrate with the arm iommu support such that multiple types
of IOMMU can be supported.
From: Nikhil Devshatwar
Create a union for all vendor specific fields and move the
amd specific fields in separate struct.
Also update the amd unit references of these fields.
This is to handle multiple iommu devices and their custom fields
separately.
Signed-off-by: Nikhil Devshatwar
---
From: Nikhil Devshatwar
J721e device has 3 instance of PVU which can be used as IOMMU.
Each PVU has a config region and a TLB region where the memory
mapping information is stored.
Describe these as part of the root cell's platform_data.
Signed-off-by: Nikhil Devshatwar
---
Notes:
Changes
From: Nikhil Devshatwar
Update the cell_state to SHUT_DOWN as part of the cell_destroy
This will make sure that the memory_unmap calls and unit's
cell_exit calls can see the correct status of the cell.
Signed-off-by: Nikhil Devshatwar
---
hypervisor/control.c | 2 ++
1 file changed, 2
From: Nikhil Devshatwar
This series adds support for TI PVU as an iommu unit.
PVU is a 2nd stage only IOMMU which provides realtime address translation.
J721e has 3 instances of PVU and all the DMA traffic can be routed via PVU
when running inside a virtual machine.
Nikhil Devshatwar (5):
From: Nikhil Devshatwar
Add stream_ids for peripherals which are behind IOMMU instances.
PVU and SMMU-V3 sets up memory mapping for all of these contexts
for correct 2nd stage translation.
Signed-off-by: Nikhil Devshatwar
---
configs/arm64/k3-j721e-evm-linux-demo.c | 7 +++
On 13/01/20 6:08 pm, Jan Kiszka wrote:
On 13.01.20 11:46, nikhil...@ti.com wrote:
From: Nikhil Devshatwar
This series adds support for TI PVU as an iommu unit.
PVU is a 2nd stage only IOMMU which provides realtime address
translation.
J721e has 3 instances of PVU and all the DMA traffic
From: Nikhil Devshatwar
Add support for Texas Instrument's Peripheral Virtualization Unit
* Define a new IOMMU type and extra fields in the platform_data
* Add new cofig option CONFIG_IOMMU_TI_PVU
* Integrate with the arm iommu support such that multiple types
of IOMMU can be supported.
On 13.01.20 13:38, Jan Kiszka wrote:
On 13.01.20 11:46, nikhil...@ti.com wrote:
From: Nikhil Devshatwar
This series adds support for TI PVU as an iommu unit.
PVU is a 2nd stage only IOMMU which provides realtime address
translation.
J721e has 3 instances of PVU and all the DMA traffic can
Branch: refs/heads/next
Home: https://github.com/siemens/jailhouse
Commit: ce9a667714d92711b7950d32b8c68dc68088a72e
https://github.com/siemens/jailhouse/commit/ce9a667714d92711b7950d32b8c68dc68088a72e
Author: Jan Kiszka
Date: 2020-01-13 (Mon, 13 Jan 2020)
Changed paths:
On 13.01.20 11:46, nikhil...@ti.com wrote:
From: Nikhil Devshatwar
This series adds support for TI PVU as an iommu unit.
PVU is a 2nd stage only IOMMU which provides realtime address translation.
J721e has 3 instances of PVU and all the DMA traffic can be routed via PVU
when running inside a
Branch: refs/heads/next
Home: https://github.com/siemens/jailhouse
Commit: 05b6322f057a4091be5323e33cec02c129c6006a
https://github.com/siemens/jailhouse/commit/05b6322f057a4091be5323e33cec02c129c6006a
Author: Nikhil Devshatwar
Date: 2020-01-13 (Mon, 13 Jan 2020)
Changed
On 13.01.20 14:09, Nikhil Devshatwar wrote:
On 13/01/20 6:08 pm, Jan Kiszka wrote:
On 13.01.20 11:46, nikhil...@ti.com wrote:
From: Nikhil Devshatwar
This series adds support for TI PVU as an iommu unit.
PVU is a 2nd stage only IOMMU which provides realtime address
translation.
J721e
On 1/12/20, 11:58 PM, "Jan Kiszka" wrote:
> On 09.01.20 16:55, Chase Conklin wrote:
>> The GICv3 architecture does not guarantee that writes to the list
>> registers are self-synchronizing. As a result, it is possible for a
>> valid interrupt to be written into a list register but have the empty
From: Jan Kiszka
There is no IOMMU support for 32-bit arm, and it's likely to now show up
there anymore. Make the iommu binding module arch-specific so that we
can add calls to the arm64 variant without affecting arm.
Signed-off-by: Jan Kiszka
---
This will go before the PVU series, and the
On 13.01.20 14:37, Jan Kiszka wrote:
On 13.01.20 13:38, Jan Kiszka wrote:
On 13.01.20 11:46, nikhil...@ti.com wrote:
From: Nikhil Devshatwar
This series adds support for TI PVU as an iommu unit.
PVU is a 2nd stage only IOMMU which provides realtime address
translation.
J721e has 3
On 13/01/20 7:07 pm, Jan Kiszka wrote:
From: Nikhil Devshatwar
Add support for Texas Instrument's Peripheral Virtualization Unit
* Define a new IOMMU type and extra fields in the platform_data
* Add new cofig option CONFIG_IOMMU_TI_PVU
* Integrate with the arm iommu support such that
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