On Sunday, October 21, 2018 at 4:57:58 AM UTC-7, J. Kiszka wrote:
> On 19.10.18 17:18, posk.de...@gmail.com wrote:
> > Hello!
> >
> > GICv3 on ARM provides the ability to route interrupts to specific cores,
> > see e.g. "Affinity routing and assignment" here:
> >
Hi,
I am using x86 i3 core processor
I have added
void vcpu_park(void)
{
#ifdef CONFIG_CRASH_CELL_ON_PANIC
- if (this_cpu_data()->failed) {
+ if (this_cpu_public()->failed) {
this_cpu_data()->vmcb.rip = 0;
return;
}
void vcpu_park(void)
Hi,
I have added
void vcpu_park(void)
{
#ifdef CONFIG_CRASH_CELL_ON_PANIC
- if (this_cpu_data()->failed) {
+ if (this_cpu_public()->failed) {
this_cpu_data()->vmcb.rip = 0;
return;
}
void vcpu_park(void)
{
#ifdef
I am trying to pass AHCI controller to non-root cell on Intel NUC7i5D. Should i
pass IOAPIC to non-root cell as well or something else to achieve that goal ?
My hardware is:
00:17.0 SATA controller: Intel Corporation Sunrise Point-LP SATA Controller
[AHCI mode] (rev 21) (prog-if 01 [AHCI
On Monday, October 22, 2018 at 2:16:17 PM UTC+8, J. Kiszka wrote:
> On 22.10.18 06:30, minskey guo wrote:
> > On Monday, October 22, 2018 at 9:46:30 AM UTC+8, minskey guo wrote:
> >> On Sunday, October 21, 2018 at 7:34:12 PM UTC+8, J. Kiszka wrote:
> >>> On 19.10.18 11:19, Jan Kiszka wrote:
>