[PATCH 1/2] arm: irqchip: add lock in irqchip_inject_pending

Thinking about core0 is inject SGI to core1, core1 is handling SGI interrupt. That means core0 might be in path to enqueue SGI into the pending_irqs array, core1 might be in path handling SGI and pick one from pending_irqs array. So need to use lock to protect unqueue, not only enqueue. Signed-of

[PATCH 2/2] arm: irqchip: drop unneeded barrier

spin_unlock implies memory barrier, no need explicit memory barrier. Signed-off-by: Peng Fan --- hypervisor/arch/arm-common/irqchip.c | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/hypervisor/arch/arm-common/irqchip.c b/hypervisor/arch/arm-common/irqchip.c index fb

RE: [PATCH 0/8] Add cache coloring support for Arm

> Subject: Re: [PATCH 0/8] Add cache coloring support for Arm > > Dear Peng, > > On Mon, Dec 02, 2019 at 02:52:04AM +, Peng Fan wrote: > > > I am reading the patchset, but this patchset could not resolve the > > > cache contention between root cell Linux and inmate cell, right? It > > > only

Re: [PATCH 1/2] arm: irqchip: add lock in irqchip_inject_pending

On 03.12.19 09:27, Peng Fan wrote: > Thinking about core0 is inject SGI to core1, core1 is handling SGI > interrupt. > > That means core0 might be in path to enqueue SGI into the pending_irqs > array, core1 might be in path handling SGI and pick one from > pending_irqs array. So need to use lock t

RE: [PATCH 1/2] arm: irqchip: add lock in irqchip_inject_pending

> Subject: Re: [PATCH 1/2] arm: irqchip: add lock in irqchip_inject_pending > > On 03.12.19 09:27, Peng Fan wrote: > > Thinking about core0 is inject SGI to core1, core1 is handling SGI > > interrupt. > > > > That means core0 might be in path to enqueue SGI into the pending_irqs > > array, core1 m

Re: [PATCH 1/2] arm: irqchip: add lock in irqchip_inject_pending

On 03.12.19 09:58, Peng Fan wrote: >> Subject: Re: [PATCH 1/2] arm: irqchip: add lock in irqchip_inject_pending >> >> On 03.12.19 09:27, Peng Fan wrote: >>> Thinking about core0 is inject SGI to core1, core1 is handling SGI >>> interrupt. >>> >>> That means core0 might be in path to enqueue SGI int

RE: [PATCH 1/2] arm: irqchip: add lock in irqchip_inject_pending

> Subject: Re: [PATCH 1/2] arm: irqchip: add lock in irqchip_inject_pending > > On 03.12.19 09:58, Peng Fan wrote: > >> Subject: Re: [PATCH 1/2] arm: irqchip: add lock in > >> irqchip_inject_pending > >> > >> On 03.12.19 09:27, Peng Fan wrote: > >>> Thinking about core0 is inject SGI to core1, cor

Re: [PATCH 1/2] arm: irqchip: add lock in irqchip_inject_pending

On 03.12.19 10:15, Peng Fan wrote: >> Subject: Re: [PATCH 1/2] arm: irqchip: add lock in irqchip_inject_pending >> >> On 03.12.19 09:58, Peng Fan wrote: Subject: Re: [PATCH 1/2] arm: irqchip: add lock in irqchip_inject_pending On 03.12.19 09:27, Peng Fan wrote: > Thinking ab