Re: [j-nsp] RSVP-TE broken between pre and post 16.1 code?

> From: Nathan Ward > Sent: Friday, August 16, 2019 11:20 AM > > Weird that the refresh timer <1200 triggers it. Do you mean the refresh timer > in the time values object is 1200 - i.e. 1.2s? JunOS default is 30,000 (30s), > 1200 > seems very short, or very long? Certainly it sounds like a bug,

[j-nsp] PFE forwarding bug - PR1380183

I hit PR1380183 last week on an MX960. https://prsearch.juniper.net/InfoCenter/index?page=prcontent =PR1380183 I currently run 17.4R2-S1.2 on all my MX960's. The PR mentions a fix in 5 different versions of Junos.

Re: [j-nsp] PCS errors with PTX box

I have a similar issue with a PTX1000 (Junos 17.3R3) , but I'm using Juniper optics (QSFP-100GBASE-LR4 on PTX1000 and CFP2-100GBASE-LR4 for the PTX5000). All the hardware has been swapped (including the PTX1000 chassis) and the errors are still incrementing. If we move the fibers from

Re: [j-nsp] PCS errors with PTX box

Not saying this is or isn't your issue, but check out KB34777. I found this the hard way with JTAC. The particular article is specific to the 3K, but the 1K may have a similar issue, and it may give you some troubleshooting leads. From: juniper-nsp on behalf

Re: [j-nsp] PFE forwarding bug - PR1380183

Unless you need some feature/function that is in some 18.x or 19.x, and everything else in 17.4 is good for you, then I would suggest using 17.4R2-S[latest], which is S6 right now. S2 and above contain the fix for this PR. My 2 cents worth. Rich Richard McGovern Sr Sales Engineer, Juniper

Re: [j-nsp] vMX and SR-IOV, VFP xml dump

Hi, On 19/08/2019 6:59 pm, adamv0...@netconsultings.com wrote: Wondering if anyone would share their xml dump from VFP -the interface config for a working SR-IOV setup please. (not sure if vCPU related info is needed as well, probably if cpu pinning is used) Sure. This is with 4 x Intel X710

[j-nsp] PCS errors with PTX box

Hey. Anyone here using PTX1Ks with multiple 100G LR4 links and third party optics? We recently started deploying a few PTX1K routers in some locations and we are getting some weird PCS errored blocks on LR4 interfaces. We haven't tested with the official Juniper QSFP28 module yet, but we tried

[j-nsp] vMX and SR-IOV, VFP xml dump

Hi folks, Wondering if anyone would share their xml dump from VFP -the interface config for a working SR-IOV setup please. (not sure if vCPU related info is needed as well, probably if cpu pinning is used) The juniper script is useless in my opinion as I'd like to understand the xml settings.

Re: [j-nsp] Rock-solid JUNOS for QFX5100

Just here to tell you that we've had an issue that sounds close to what you saw: After a commit, a LAG would stop moving packets. Renaming the LAG (i.e. from ae24 to ae35) would fix the issue. Renaming it back to ae24 would trigger the issue again. Happened on a device that was only used for